Secondary Registers for Test and De-Bugging MT312
10.2.43 Byte Align Set up. Register 95 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
BA SETUP
95
BA FSM[1:0]
BA MV[1:0]
BA UNLK[3:0]
R/W
D4
B7-6:
BA FSM[1:0]
Byte Align FSM mode.
B5-4:
B3-0:
MA MV[2:0] + 5 =
BA UNLK[3:0] +3 =
Byte Align majority voting.
Number of bad sync words to unlock the Byte Align. The default
register value of 4 is equivalent to 7 bad sync words.
10.2.44 Program Synchronising Byte. Register 98 (R/W)
PROG SYNC (98)
Default value
71 dec.
47 hex.
PROG SYNC[7:0 ]
If FEC SETUP[2] is high, use the PROG SYNC value to
synchronise MPEG data packets.
10.2.45 AFC Frequency Search Threshold. Register 99 (R/W)
AFC SEAR TH (99)
Default value
35 dec.
23 hex.
20 hex.
AFC SEAR TH[7:0]
10.2.46 Accumulator Differential Threshold. Register 100 (R/W)
CSACC DIFF TH (100)
Default value
32 dec.
CSACC DIFF TH[7:0]
10.2.47 QPSK Lock Control. Register 101 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
QPSK LK CT
101
CS
L LK
TS
L LK
ACC
CK
NUM PLD INT[4:0]
R/W
04
B7:
CS L LK
TS L LK
ACC CK
High = Use CS long lock.
B6:
High = Use TS long lock.
B5:
High = Disable Accumulator check option.
Maximum value allowed is 29.
B4-0:
NUM PLD INT[4:0]
71
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