Secondary Registers for Test and De-Bugging MT312
10.2.25 Phase Lock Detect Threshold out of lock. Registers 69 - 72 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
PLD OUTLK3
69
SW R N MX[1:0]
PLD OUTLK3[9:4]
R/W
AE
PLD OUTLK2
PLD OUTLK1
70
71
PLD OUTLK3[3:0]
PLD OUTLK2[9:6]
R/W
R/W
E6
40
PLD OUTLK2[5:0]
PLD O
LK1[9:8]
PLD OUTLK0
72
PLD OUTLK1[7:0]
R/W
7E
B31-30:
SW R N MX[1:0]
CS Sweep rate number max.
B29-20:
B19-10:
B9-0:
PLD OUTLK TH3[9:0]
PLD OUTLK TH2[9:0]
PLD OUTLK TH1[9:0]
10.2.26 Phase Lock Detect Threshold in lock. Registers 73 - 76 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
PLD INLK3
PLD INLK2
PLD INLK1
73
74
75
Reserved
R/W
R/W
01
A0
68
PLD INLK3[3:0]
PLD INLK2[5:0]
PLD INLK2[9:6]
PLD INLK1
[9:8]
PLD INLK0
76
PLD INLK1[7:0]
R/W
1A
B31-30:
Reserved
B29-20:
B19-10:
B9-0:
PLD INLK TH3[9:0]
PLD INLK TH2[9:0]
PLD INLK TH1[9:0]
10.2.27 Phase Lock Detect Accumulator Time. Register 77 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
PLD ACC
TIME
77
CS PLD MPLEN[3:0]
LOSSLOCK INT SW[3:0]
R/W
48
B7-4:
B3-0:
CS PLDMPLEN[3:0]
Maximum value allowed is 8.
LOSSLOCK INT SW[3:0]
67
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