MT312 Secondary Registers for Test and De-Bugging
10.2.35 Viterbi Reference Byte 0. Register 87 (R/W)
VIT REF0 (87)
Default value
128 dec.
20 dec.
10 dec.
6 dec.
80 hex.
14 hex.
0A hex.
06 hex.
04 hex.
02 hex.
VIT REF0[7:0]
Viterbi reference byte 0.
10.2.36 Viterbi Reference Byte 1. Register 88 (R/W)
VIT REF1 (88)
Default value
VIT REF1[7:0]
Viterbi reference byte 1.
10.2.37 Viterbi Reference Byte 2. Register 89 (R/W)
VIT REF2 (89)
Default value
VIT REF2[7:0]
Viterbi reference byte 2.
10.2.38 Viterbi Reference Byte 3. Register 90 (R/W)
VIT REF3 (90) Default value
VIT REF3[7:0] Viterbi reference byte 3.
10.2.39 Viterbi Reference Byte 4. Register 91 (R/W)
VIT REF4 (91)
Default value
4 dec.
VIT REF4[7:0] Viterbi reference byte 4.
10.2.40 Viterbi Reference Byte 5. Register 92 (R/W)
VIT REF5 (92)
Default value
2 dec.
VIT REF5[7:0] Viterbi reference byte 5.
10.2.41 Viterbi Reference Byte 6. Register 93 (R/W)
VIT REF6 (93)
Default value
1 dec.
01 hex.
94 hex.
VIT REF6[7:0] Viterbi reference byte 6.
10.2.42 Viterbi Maximum Error. Register 94 (R/W)
VIT MAXERR (94)
Default value
148 dec.
VIT MAXERR[7:0]Viterbi maximum error.
This register controls the frequency of the BER indication audio signal, output on the status pin when the FEC
STAT EN register B0 is set high, see pages 11 and 50.
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