Secondary Registers for Test and De-Bugging MT312
10.2.32 Loss Lock Time. Register 82 (R/W)
LOSSLOCK TM (82)
Default value
16 dec.
10 hex.
LOSSLOCK TM[7:0]
After the FEC locks it can unlock due to a signal fade or a cycle slip. Then the QPSK allows the following
number of symbol periods for the FEC to regain lock :
LOSSLOCK TM * 262144
If the FEC does not regain lock during this number of symbol periods, then QPSK will re-acquire lock.
10.2.33 Viterbi Error Period. Registers 83 - 85 (R/W)
VIT ERRPER (83, 84 & 85)
Default value
16,777,215 dec.FF FF FF hex.
VIT ERRPER
[23:0]
Viterbi error period. This is the period over which the Viterbi error count is measured. See
registers 11, 12 & 13 on page 53.
10.2.34 Viterbi Set up. Register 86 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
VIT SETUP
86
FR AL TM
O[1:0]
SRCH CYC
[1:0]
SEARCH START
[2:0]
EX F
LK
R/W
34
B7-6:
FR AL TM O [1:0]
SRCH CYC[2:0]
Frame (or byte) align time out.
B5-4:
B3-1:
Viterbi BER based search cycles.
SEARCH START[2:0]
Code rate search start, only one code rate may be selected.
Code rate search start
B6-4
at:
0
1
2
3
4
5
1/2
2/3
3/4
5/6
6/7
7/8
Table 7 - Viterbi code rate search start
B0:
EX F LK
Exit false lock.
69
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