MT312 Secondary Registers for Test and De-Bugging
10.2.48 QPSK State Control. Register 102 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
QPSK ST CT
102
HLD
ST
AFC
RS
M S
RS
NXT
FR
FCE
ST
FORCED ST[2:0]
R/W
00
B7:
HLD ST
AFC RS
M S RS
NXT FR
FCE ST
High = Hold state.
High = AFC reset.
B6:
B5:
High = Mixer scan reset.
High = Get next frequency.
High = Force state.
Forced state.
B4:
B3:
B2-0:
FORCED ST[2:0]
10.2.49 QPSK Reset. Register 104 (R/W)
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
QPSK RESET
104
Reserved
REL
QP
PR
QP
PR
CS
PR
TS
PR
FE
PR
AGC
R/W
00
B7-6:
Reserved Must be set low.
B5:
B4:
B3:
B2:
B1:
B0:
REL QP
PR QP
PR CS
PR TS
High = Release QPSK FSM.
High = Partial reset FSM (applies to QPSK control).
High = Partial reset carrier synchroniser
High = Partial reset timing synchroniser (includes fine AGC).
High = Partial reset front-end logic.
PR FE
PR AGC
High = Partial reset analogue AGC.
10.2.50 QPSK Test Control. Register 105 (R/W)
QPSK TST CT (105)
Default value
0 dec.
00 hex.
QPSK TEST CTRL[7:0]
For factory test purposes only.
72
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
