Le77D11
Data Sheet
For this application, R
BD
is 180
Ω
and capacitor C
BD
is 27 nF to increase the switching speed and efficiency. This increases the
power available during the Ringing state when the converter operates at the highest currents. The capacitors C
FL
and C
VREG
use
very low ESR film capacitors to minimize ripple and noise on V
REG
. The capacitance is sized to permit more rapid charging of the
capacitors, and hence a faster slew rate. Reduction of switcher noise is accomplished by using lower ESR capacitors and
increasing the value of the L
VREG
inductor in the post filter. The power supply output is able to track the ringing waveform under
these conditions.
Figure 6.
Switching Power Supply Block Diagram
V
SW
VSW
LEADING
EDGE
BLANKING
FILTER
SET
-
RESET
100 Vin In Ringing
800 K
V
REF
1.4 V
CLAMP
-
+
COMPARATOR
TRIANGLE
WAVE
DRIVER
+
0.28 V
Inside Le77D11 SLIC Device
-
+
C
SW
C
SWi
*
BGND
V
CC
LATCH
48 V
800 K
In Active
OUTPUT
-
+
R
LIMi
*
8V
I=
800 K
ILS
i
in Active
I=
15 V
800 K
C
BDi
*
V
SW
SD
i
R
BDi
*
D
D2
*
Q
SWi
*
in Ringing
CHS
i
D
SWi
*
C
FLi
*
C
HSi
*
FSET
R
RAMP
*
CHCLK
L
SWi
*
BGND
BGND
800 k
10% High Duty Cycle
85.3 kHz or 256 kHz
Selectable via the Le78D11 device
L
VREGi
*
VREG
i
C
VREGi
* C
VREGi
*
C
ESRi
*
BGND
BGND
Note:
* denotes external components
Signal Transmission
In Normal Active and Reverse Polarity states, the AC line current is sensed across the internal resistors, R
S
(see
summed, attenuated and converted to voltage at the CFILT pin. This voltage then goes
through a high pass filter (with a nominal 13 Hz corner frequency), implemented using an on-chip 8 kΩ nominal resistor and an
external C
HP
capacitor, is amplified, and sent to the Le78D11 VoSLAC device at the VOUT pin. The output is proportional to the
AC metallic component of the line voltage. Additionally, the signal transmission block receives the analog signal from the
Le78D11 VoSLAC device. The analog signal is amplified and sent to the line.A proportion of the signal at V
OUT
is also fed back
to the line.
There are three parameters which define the AC characteristics of the Le77D11 VoSLIC device. First is the input impedance
presented to the line or two-wire side (Z
2WIN
), second is the gain from the four-wire (V
IN
) to the two-wire (V
AB
) side (G
42
), and
third is the gain from the two-wire side to the four-wire (V
OUT
) side (G
24
).
Input Impedance (Z
2WIN
)
Z
2WIN
is the impedance presented to the line at the two-wire side, and is defined by:
Z
2WIN
= 2R
F
+
K
V
K
OUT
R
IMT
7
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
