Le77D11
Figure 5.
V
REF
+ V
PK
Data Sheet
Ringing Waveforms
V
REF
V
REF
– V
PK
A. Voltage Applied to VIN Pin
–4 V
–(K
R
• V
PK
+ 4)
B. Voltage Output at A (Tip) (dashed line) and B (Ring) (solid line) Pins
Switcher Controller
The switcher controller’s main function is to provide a negative power supply (V
REG
) that tracks Tip and Ring voltage for the two-
wire interface. As Tip and Ring voltage decreases, the switcher will likewise lower V
REG
. In doing so, the switcher saves power
because the device is not forced to maintain static supply voltage in all states.
The switching power supply controller uses a discontinuous mode buck-boost voltage converter topology. The frequency of
operation is programmed by the Le78D11 VoSLAC device and is typically 85.3 kHz (256 kHz/3). The Le78D11 VoSLAC device
outputs a clock at its programmed frequency with approximately a 10% duty cycle which is fed into the CHCLK pin of the Le77D11
VoSLIC device. This clock signal controls the switching supply's operating frequency as well as the switching supply's maximum
duty cycle. The Le77D11 VoSLIC device adjusts the actual duty cycle up to the maximum of 90% depending on the magnitude
of the error voltage on the compensation (CHS) pin. The error signal is generated by integrating the difference in control current
which is set by the Le77D11 VoSLIC device, and the feedback current. This error signal will converge to a value which in turn
sets the duty cycle of the switching supply to satisfy feedback loop requirements.
A control current (See
is generated on the Le77D11 VoSLIC device
and is set to force V
REG
to track Tip and Ring line conditions to optimize system power efficiency. In equilibrium, the control
current, which is fed into the CHS summing node, is set to provide the required line voltage plus an offset to give headroom for
the power amplifiers.
The error signal on CHS is compared to an internal ramp signal. The ramp rate of this internal ramp signal is set by a resistor,
R
RAMP
, to analog ground (AGND) on the FSET pin. A 1% resistor should be chosen to give the ramp precise control, and prevent
internal nodes from going into saturation. R
RAMP
is determined by the equation: R
RAMP
= (24 • 10
9
Ω-Hz)/(CHCLK
Frequency).
When the CHCLK signal goes from a logic high to a logic low, it will initiate a cycle by resetting the ramp, resetting a current limit
latch, and turning on the external power switch. Then, on a cycle-by-cycle basis, one of three events will shut off the power switch
depending on which event occurs first:
a) The ramp voltage exceeds the error voltage that is integrated on the CHS node (normal voltage feedback operation).
b) The CHCLK goes high (90% duty cycle point is reached).
c) The power switch current limit threshold is reached.
Cycle-by-cycle current limiting is provided by the current sense ILS pin which senses the external power switch current through
the resistor R
LIM
. If this pin exceeds
−0.28
V with respect to V
SW
, the switching supply will set the current limit latch and shut off
the external switch drive until the CHCLK pin goes high to reset the latch. This peak inductor current, and also peak switching
converter power output can be controlled on a cycle-by-cycle basis and set by the equation I
LIM
= |0.28 V|/R
LIM
.
This sensing configuration has the added benefit that if the clock signal is removed for some reason, the power switch cannot be
left on indefinitely.
A leading edge blanking filter is added at the output of the latch to ignore the first 150 ns of a current limit event. This feature is
used to ignore a false current trip that may be caused by the power switch driving the reverse recovery charge (Q
RR
) of the
external power rectifier.
This circuit has been optimized for operation to supply 20-Hz ringing of 90-V peak with a nominal supply voltage, V
SW
, of 12 V.
The on chip driver is designed to drive an external PNP transistor. Its output drive is clamped between 7-9 V below V
SW
, and can
source or sink approximately 100 mA. The driver has approximately 50
Ω
of source resistance. When a PNP transistor is used,
additional resistance should be added from the SD
i
pin to the base of the external power device.
6
Zarlink Semiconductor Inc.
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