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GP2021/IG/GQ1Q 参数 Datasheet PDF下载

GP2021/IG/GQ1Q图片预览
型号: GP2021/IG/GQ1Q
PDF下载: 下载PDF文件 查看货源
内容描述: [Correlator, 16-Bit, CMOS, PQFP80, 14 X 14 MM, 2 MM HEIGHT, MS-022BC, MQFP-80]
分类和应用: 时钟外围集成电路
文件页数/大小: 63 页 / 511 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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GP2021  
61, 62, 63, 66  
16-BIT ACCUMULATE  
AND DUMP - Q_TRACKING  
16-BIT ACCUMULATE  
AND DUMP - Q_PROMPT  
CODE  
SLEW  
61  
61, 63  
61, 62  
61, 0  
C/A CODE  
GENERATOR  
SIGN 0  
AND  
MAG 0  
IN AND OUT  
DATA BUSES  
CODE  
PHASE  
COUNTER  
SOURCE  
SELECTOR  
SIGN 0  
AND  
MAG 0  
CODE  
DCO  
CARRIER  
DCO  
SELECT  
SOURCE  
AND  
SELECT  
MODE  
CARRIER  
CYCLE  
COUNTER  
EPOCH  
COUNTERS  
DUMP  
ACCUMS, CODE PHASE, ETC.  
16-BIT ACCUMULATE  
AND DUMP - I_PROMPT  
16-BIT ACCUMULATE  
AND DUMP - I_TRACKING  
Figure 5 Tracking module block diagram  
The indvidual sub-blocks in the tracking modules are:  
As the clock to the DCO is normally less than 8 times the  
output frequency, not all phases are generated in every  
cycle. With a typical clock frequency of 5·714 MHz and an  
output frequency of 1·405 MHz there are only about  
4 phases per cycle. These will slide through the cycle as  
time progresses to cover all values.  
Carrier DCO  
The Carrier DCO, which is clocked at the SAMPCLK  
frequency, isusedtosynthesisethedigitallocaloscillatorsignal  
required to bring the input signal to baseband in the mixer  
block, and must be adjusted away from its nominal value to  
allow for Doppler shift and reference frequency error.  
Code DCO  
The Code DCO is similar to the Carrier DCO block. It is  
also clocked at the SAMPCLK frequency and synthesises  
the oscillator required to drive the code generator at twice  
the required chipping rate. The nominal frequency of the  
output is 2·046 MHz, to give a chip rate of 1·023 MHz and  
When used with the GP2015/GP2010 the nominal  
frequency of this signal is 1·405396825 MHz (with a  
resolution of 42·57475mHz) and is set by loading the 26-  
bit register CHx_CARRIER_DCO_INCR. This very fine  
resolution is required so that the DCO will stay in phase  
with the satellite signal for an adequate time. The Carrier  
DCO Phase cannot be directly set, but must be adjusted  
by altering the frequency.  
is  
set  
by  
loading  
the  
25-bit  
register  
CHx_CODE_DCO_INCR.  
It is programmed with a resolution of 85·14949 mHz when  
used with a GP2015/GP2010 front end. Again, the very  
fine resolution is needed to keep the DCO in phase with  
the satellite signal. The Code DCO Phase can only be set  
to the exact satellite phase in Preset mode. In Update  
mode, it must be aligned with the satellite phase by  
adjusting its frequency.  
The Carrier DCO outputs are 4-level, 8-phase sinusoids  
with the sequences over one cycle as shown in Table 4.  
Sequence  
Destination Arm  
ILO  
QLO  
21 11 12 12 11 21 22 22  
12 12 11 21 22 22 21 11  
Table 4 Carrier DCO outputs  
9
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