欢迎访问ic37.com |
会员登录 免费注册
发布采购

GP2021/IG/GQ1Q 参数 Datasheet PDF下载

GP2021/IG/GQ1Q图片预览
型号: GP2021/IG/GQ1Q
PDF下载: 下载PDF文件 查看货源
内容描述: [Correlator, 16-Bit, CMOS, PQFP80, 14 X 14 MM, 2 MM HEIGHT, MS-022BC, MQFP-80]
分类和应用: 时钟外围集成电路
文件页数/大小: 63 页 / 511 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第1页浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第2页浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第3页浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第4页浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第6页浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第7页浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第8页浏览型号GP2021/IG/GQ1Q的Datasheet PDF文件第9页  
GP2021  
Description  
Pin  
Signal name  
Type  
ARM system mode  
Standard interface mode  
24  
ACCUM_INT  
O
A free running interrupt to the microprocessor. It allows control of data transfer  
between the accumulators in the correlator and the microprocessor. It is active  
low when configured for ARM System mode or Motorola mode and is active high  
in Intel mode.  
25  
26  
27  
MEAS_INT  
O
I
An interrupt to the microprocessor. It allows control of measurement data transfer  
between the correlator and the microprocessor. It is active Low when configured  
for ARM System mode or Motorola mode and is active High in Intel mode.  
NBW/WRPROG  
NMREQ/DISCIP2  
Byte/Word  
microprocessor. Low indicates a byte mode, High selects 486 interface and  
transfer, and high a word transfer. low 186 style. Unused in Motorola mode  
input  
from  
the Write-Read Program input. In Intel  
I
Memory Request input from the Multi-purpose discrete input.  
microprocessor. Low indicates that the  
microprocessor requires a memory  
access during the following cycle.  
28  
NOPC/NINTELMOT  
I
Opcode fetch input from the High selects Motorola mode and low  
microprocessor. Low indicates that an Intel mode.  
instruction is being fetched and igh that  
data is being transferred.  
Read/Write Select input from the Multi-purpose discrete input.  
microprocessor. Low indicates a read  
cycle and high a write cycle.  
Microprocessor Clock output (nominally Unused output (do not connect).  
20MHz). Its phases can be stretched  
29  
30  
NRW/DISCIP3  
MCLK/NC  
I
O
under control of the Microprocessor  
Interface.  
31  
ABORT/MICRO_CLK  
O
Abort output to the microprocessor. 20MHz Clock output. Provides a 20MHz  
Generates a valid ARM Data Abort clock with a 1:1 mark-to-space ratio.  
sequence, triggered by a rising edge at  
MULTI_FN_IO if this function is enabled.  
Multi-purpose discrete input/output. After a GP2021 reset it is configured as an  
input.  
Address input from the microprocessor. Read input from the microprocessor. In  
A<22:20> are decoded to select the Intel mode it is the active low read strobe.  
32  
33  
DISCIO  
I/O  
I
A22/READ  
address space partitioning.  
In Motorola mode it is the Read (high)/  
Write (low) select line.  
36  
37  
A21/NCS  
I
I
Address input from the microprocessor. GP2021 Chip Select input (active low).  
A<22:20> are decoded to select the  
address space partitioning.  
Address input from the microprocessor Write-Read Strobe input from the  
A<22:20> are decoded to select the microprocessor. In Intel mode it is the  
A20/WREN  
address space partitioning.  
active low write strobe. In Motorola mode  
it is the active high Write-Read strobe.  
38-45  
46  
A<9:2>  
A1/ALE_IP  
I
I
Address Inputs <9:2> from the microprocessor. These allow register selection.  
Address input 1 from the micro- Address Latch Enable input from  
processor. A<1:0> are decoded to microprocessor (active high)  
provide individual byte write selection via  
NW<3:0>.  
47  
A0/NRESET_IP  
I
Address input 0 from the micro- Reset input (active low).  
processor. A<1:0> are decoded to  
provide individual byte write selection via  
NW<3:0>.  
Table 2 Pin descriptions (continued)  
cont…  
5
 复制成功!