R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3
-4
Symbol
Write Operation Description
Size
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
Min
14.4
14.4
7.2
7.2
2.4
2.4
0
Max
Min
15.0
15.0
7.5
7.5
2.8
2.8
0
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
Address write cycle time (clock K period)
-
-
WCS
T
T
-
-
WCTS
T
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
1 ms
1 ms
WPS
1 ms
1 ms
WPTS
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ASS
T
-
ASTS
T
-
AHS
T
0
0
-
AHTS
T
D
D
setup time before clock K
hold time after clock K
3.2
1.9
0
3.5
2.5
0
-
DSS
IN
IN
T
-
DSTS
T
-
DHS
T
0
0
-
DHTS
T
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
2.0
2.0
0
2.2
2.2
0
-
WSS
T
T
T
-
-
WSTS
T
WHS
0
0
-
WHTS
T
8.8
10.3
-
10.3
11.6
WOS
-
WOTS
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3
-4
(1)
Symbol
Write Operation Description
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
Size
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Min
14.4
7.2
2.5
0
Max
Min
15.0
7.5
2.8
0
Max
Units
ns
T
T
WCDS
WPDS
1 ms
1 ms
ns
T
-
-
ns
ASDS
T
-
-
ns
AHDS
T
T
D
D
setup time before clock K
hold time after clock K
2.5
0
-
2.2
0
-
ns
DSDS
DHDS
WSDS
WHDS
WODS
IN
IN
-
-
-
ns
T
T
T
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
1.8
0
2.2
0.3
-
-
-
ns
-
ns
-
7.8
10.0
ns
Notes:
1. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
DS021 (v2.2) June 25, 2000
www.xilinx.com
9
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
