R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E CLB Switching Characteristic Guidelines (continued)
-3
-4
Symbol
Description
Min
Max
Min
Max
Units
Hold Time after Clock K
T
F/G inputs
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CKI
T
F/G inputs via H
CKIH
T
T
T
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN/H2
CKHH0
CKHH1
CKHH2
T
CKDI
T
C inputs via EC
CKEC
T
C inputs via SR, going Low (inactive)
CKR
Clock
T
Clock High time
Clock Low time
4.0
4.0
-
-
4.5
4.5
-
-
ns
ns
CH
T
CL
Set/Reset Direct
T
Width (High)
4.0
-
-
5.5
-
-
ns
ns
RPW
T
Delay from C inputs via S/R, going High to Q
4.0
6.5
RIO
(1)
Master Set/Reset
T
Width (High or Low)
11.5
-
13.0
-
ns
ns
MRW
T
Delay from Global Set/Reset net to Q
Global Set/Reset inactive to first active clock K edge
-
-
-
18.7
18.7
125
-
-
-
23.0
23.0
111
MRQ
T
ns
MRK
TOG
(2)
F
Toggle Frequency
MHz
Notes:
1. Timing is based on the XC4005E. For other devices see the static timing analyzer.
2. Export Control Max. flip-flop toggle rate.
8
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
