R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Note: -3 Speed Grade only applies to XQ4010E and
XQ4013E Plastic Package options only. -4 Speed Grade
applies to all XQ devices and is only available in
Ceramic Packages only.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
XQ4000E Global Buffer Switching Characteristics
(1)
(2)
-3
-4
Symbol
Description
Device
Max
-
Max
7.0
Units
ns
T
From pad through primary buffer, to any clock K
XQ4005E
XQ4010E
XQ4013E
XQ4025E
XQ4005E
XQ4010E
XQ4013E
XQ4025E
PG
6.3
6.8
-
11.0
11.5
12.5
7.5
ns
ns
ns
T
From pad through secondary buffer, to any clock K
-
ns
SG
6.8
7.3
-
11.5
12.0
13.0
ns
ns
ns
Notes:
1. For plastic package options only.
2. For ceramic package options only.
4
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
