R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
CLB Switching Characteristics
-4
Symbol
Description
Min
Max
Units
Combinatorial Delays
T
F/G inputs to X/Y outputs
-
-
-
-
-
-
-
2.2
3.8
3.2
3.6
3.0
3.6
2.0
ns
ns
ns
ns
ns
ns
ns
ILO
T
F/G inputs via H’ to X/Y outputs
IHO
T
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
ITO
T
HH0O
HH1O
HH2O
CBYP
T
T
T
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
T
-
-
-
-
-
-
2.5
4.1
ns
ns
ns
ns
ns
ns
OPCY
OUT
T
Add/Subtract input (F3) to C
OUT
ASCY
T
Initialization inputs (F1, F3) to C
1.9
INCY
OUT
T
C
C
through function generators to X/Y outputs
3.0
SUM
IN
IN
T
T
to C
, bypass function generators
OUT
0.60
0.18
BYP
Carry net selay, C
to C
IN
NET
OUT
Sequential Delays
T
Clock K to flip-flop outputs Q
Clock K to latch outputs Q
-
-
2.2
2.2
ns
ns
CKO
T
CKLO
Setup Time before Clock K
T
F/G inputs
1.3
3.0
2.8
2.2
2.8
1.2
1.2
0.8
2.2
3.9
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICK
T
F/G inputs via H
IHCK
T
T
T
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
HH0CK
HH1CK
HH2CK
T
DICK
T
C inputs via EC
ECCK
T
C inputs via S/R, going Low (inactive)
CIN input via F/G
RCK
T
CCK
T
CIN input via F/G and H
CHCK
Hold Time after Clock K
F/G inputs
T
0
-
ns
CKI
DS021 (v2.2) June 25, 2000
www.xilinx.com
21
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
