R
QPRO XQ4000E/EX QML High-Reliability FPGAs
CLB Switching Characteristics (Continued)
-4
Symbol
Description
Min
0
Max
Units
ns
T
F/G inputs via H
-
-
-
-
-
-
-
CKIH
T
T
T
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
0
ns
CKHH0
CKHH1
CKHH2
0
ns
0
ns
T
0
ns
CKDI
T
C inputs via EC
0
ns
CKEC
T
C inputs via SR, going Low (inactive)
0
ns
CKR
Clock
T
Clock High time
Clock Low time
3.5
3.5
-
-
ns
ns
CH
T
CL
Set/Reset Direct
T
Width (High)
3.5
-
-
ns
ns
RPW
T
Delay from C inputs via S/R, going High to Q
4.5
RIO
Global Set/Reset
T
Minimum GSR pulse width
-
-
-
13.0
22.8
143
ns
MRW
T
Delay from GSR input to any Q
Toggle frequency (MHz) (for export control)
MRQ
F
MHz
TOG
22
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DS021 (v2.2) June 25, 2000
Product Specification
XILINX [ XILINX, INC ]
