R
Spartan-II FPGA Family: DC and Switching Characteristics
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in "IOB Output Delay Adjustments for Different Standards," page 59.
Speed Grade
-6
-5
Symbol
Propagation Delays
TIOOP
Description
Min
Max
Min
Max Units
O input to pad
-
-
2.9
3.4
-
-
3.4
4.0
ns
ns
TIOOLP
O input to pad via transparent latch
3-state Delays
TIOTHZ
T input to pad high-impedance(1)
-
-
-
-
-
2.0
3.0
2.5
3.5
5.0
-
-
-
-
-
2.3
3.6
2.9
4.2
5.9
ns
ns
ns
ns
ns
TIOTON
T input to valid data on pad
TIOTLPHZ
T input to pad high impedance via transparent latch(1)
T input to valid data on pad via transparent latch
GTS to pad high impedance(1)
TIOTLPON
TGTS
Sequential Delays
TIOCKP
Clock CLK to pad
Clock CLK to pad high impedance (synchronous)(1)
-
-
-
2.9
2.3
3.3
-
-
-
3.4
2.7
4.0
ns
ns
ns
TIOCKHZ
TIOCKON
Clock CLK to valid data on pad (synchronous)
Setup/Hold Times with Respect to Clock CLK(2)
TIOOCK / TIOCKO O input
1.1 / 0
-
-
1.3 / 0
-
-
ns
ns
TIOOCECK
TIOCKOCE
TIOSRCKO
TIOCKOSR
TIOTCK / TIOCKT 3-state setup times, T input
/
OCE input
0.9 / 0.01
0.9 / 0.01
/
SR input (OFF)
1.2 / 0
-
1.3 / 0
-
ns
0.8 / 0
1.0 / 0
-
-
0.9 / 0
1.0 / 0
-
-
ns
ns
TIOTCECK
TIOCKTCE
TIOSRCKT
TIOCKTSR
/
3-state setup times, TCE input
/
3-state setup times, SR input (TFF)
1.1 / 0
-
1.2 / 0
-
ns
Set/Reset Delays
TIOSRP
SR input to pad (asynchronous)
SR input to pad high impedance (asynchronous)(1)
SR input to valid data on pad (asynchronous)
GSR to pad
-
-
-
-
3.7
3.1
4.1
9.9
-
-
-
-
4.4
3.7
ns
ns
ns
ns
TIOSRHZ
TIOSRON
4.9
TIOGSRQ
11.7
Notes:
1. Three-state turn-off delays should not be adjusted.
2. A zero hold time listing indicates no hold time or a negative hold time.
DS001-3 (v2.8) June 13, 2008
Product Specification
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