R
Spartan-II FPGA Family: Functional Description
Revision History
Date
Version
2.0
Description
09/18/00
03/05/01
09/03/03
Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description.
Clarified guidelines for applying power to VCCINT and VCCO
The following changes were made:
2.1
2.2
•
•
"Serial Modes," page 20 cautions about toggling WRITE during serial configuration.
Maximum VIH values in Table 32 and Table 33 changed to 5.5V.
•
•
•
In "Boundary Scan," page 13, removed sentence about lack of INTEST support.
In Table 9, page 17, added note about the state of I/Os after power-on.
In "Slave Parallel Mode," page 23, explained configuration bit alignment to SelectMap
port.
06/13/08
2.8
Added note that TDI, TMS, and TCK have a default pull-up resistor. Added note on maximum
daisy chain limit. Updated Figure 15 and Figure 18 since Mode pins can be pulled up to either
2.5V or 3.3V. Updated DLL section. Recommended using property or attribute instead of
primitive to define I/O properties. Updated description and links. Updated all modules for
continuous page, figure, and table numbering. Synchronized all modules to v2.8.
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 2 of 4
50
XILINX [ XILINX, INC ]
