R
Spartan-II FPGA Family: Functional Description
SSTL2_I
SSTL2 Class II
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in Figure 49. DC voltage specifications
appear in Table 27 for the SSTL2_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in Figure 50. DC voltage specifications
appear in Table 28 for the SSTL2_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL2 Class I
SSTL2 Class II
V
= 1.25V
V
= 1.25V
V
= 1.25V
TT
TT
TT
V
= 2.5V
V
= 2.5V
CCO
CCO
50Ω
50Ω
50Ω
25Ω
25Ω
Z = 50
Z = 50
V
= 1.25V
V
= 1.25V
REF
REF
DS001_49_061200
DS001_50_061200
Figure 49: Terminated SSTL2 Class I
Table 27: SSTL2_I Voltage Specifications
Figure 50: Terminated SSTL2 Class II
Table 28: SSTL2_II Voltage Specifications
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
1.35
1.39
3.0(2)
1.17
-
Parameter
Min
2.3
Typ
2.5
1.25
1.25
1.43
1.07
-
Max
2.7
1.35
1.39
3.0(2)
1.17
-
VCCO
VCCO
V
REF = 0.5 × VCCO
TT = VREF + N(1)
1.15
1.11
1.33
–0.3(3)
1.76
-
V
REF = 0.5 × VCCO
TT = VREF + N(1)
1.15
1.11
1.33
–0.3(3)
1.95
-
V
V
VIH ≥ VREF + 0.18
VIL ≤ VREF – 0.18
VOH ≥ VREF + 0.61
VOL ≤ VREF – 0.61
VIH ≥ VREF + 0.18
VIL ≤ VREF – 0.18
VOH ≥ VREF + 0.8
VOL ≤ VREF - 0.8
-
0.74
-
-
0.55
-
I
OH at VOH (mA)
OL at VOL (mA)
–7.6
7.6
-
I
OH at VOH (mA)
OL at VOL (mA)
–15.2
15.2
-
I
-
-
I
-
-
Notes:
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. VIH maximum is VCCO + 0.3.
2. VIH maximum is VCCO + 0.3.
3.
VIL minimum does not conform to the formula.
3.
VIL minimum does not conform to the formula.
DS001-2 (v2.8) June 13, 2008
Product Specification
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