R
Spartan-II FPGA Family: Functional Description
SSTL3 Class I
SSTL3 Class II
A sample circuit illustrating a valid termination technique for
SSTL3_I appears in Figure 47. DC voltage specifications
appear in Table 25 for the SSTL3_I standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
A sample circuit illustrating a valid termination technique for
SSTL3_II appears in Figure 48. DC voltage specifications
appear in Table 26 for the SSTL3_II standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
SSTL3 Class I
SSTL3 Class II
V
= 1.5V
V
= 1.5V
V
= 1.5V
TT
TT
TT
V
= 3.3V
V
= 3.3V
CCO
CCO
50Ω
50Ω
50Ω
25Ω
25Ω
Z = 50
Z = 50
V
= 1.5V
V
= 1.5V
REF
REF
DS001_47_061200
DS001_48_061200
Figure 47: Terminated SSTL3 Class I
Table 25: SSTL3_I Voltage Specifications
Figure 48: Terminated SSTL3 Class II
Table 26: SSTL3_II Voltage Specifications
Parameter
Min
3.0
1.3
1.3
1.5
–0.3(2)
1.9
-
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
1.7
1.7
3.9(1)
1.5
-
Parameter
Min
3.0
1.3
1.3
1.5
–0.3(2)
2.1
-
Typ
3.3
1.5
1.5
1.7
1.3
-
Max
3.6
1.7
1.7
3.9(1)
1.5
-
VCCO
VCCO
V
REF = 0.45 × VCCO
V
REF = 0.45 × VCCO
V
TT = VREF
V
TT = VREF
VIH ≥ VREF + 0.2
VIL ≤ VREF – 0.2
VOH ≥ VREF + 0.6
VOL ≤ VREF – 0.6
VIH ≥ VREF + 0.2
VIL ≤ VREF – 0.2
VOH ≥ VREF + 0.8
VOL ≤ VREF – 0.8
-
1.1
-
-
0.9
-
I
OH at VOH (mA)
OL at VOL (mA)
–8
-
I
OH at VOH (mA)
OL at VOL (mA)
–16
16
-
I
8
-
-
I
-
-
Notes:
Notes:
1. VIH maximum is VCCO + 0.3.
1. VIH maximum is VCCO + 0.3
2. VIL minimum does not conform to the formula.
2. VIL minimum does not conform to the formula
DS001-2 (v2.8) June 13, 2008
Product Specification
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