R
Spartan-II FPGA Family: Functional Description
HSTL Class III
HSTL Class IV
A sample circuit illustrating a valid termination technique for
HSTL_III appears in Figure 45. DC voltage specifications
appear in Table 23 for the HSTL_III standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics.
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in Figure 46.DC voltage specifications
appear in Table 23 for the HSTL_IV standard. See "DC
Specifications" in Module 3 for the actual FPGA
characteristics
HSTL Class III
HSTL Class IV
V
= 1.5V
V
= 1.5V
V
= 1.5V
TT
TT
TT
V
= 1.5V
V
= 1.5V
CCO
CCO
50Ω
50Ω
50Ω
Z = 50
Z = 50
V
= 0.9V
V
= 0.9V
REF
REF
DS001_45_061200
DS001_46_061200
Figure 46: Terminated HSTL Class IV
Figure 45: Terminated HSTL Class III
Table 23: HSTL Class III Voltage Specification
Table 24: HSTL Class IV Voltage Specification
Parameter
VCCO
Min
Typ
Max
Parameter
VCCO
Min
Typ
Max
1.40
1.50
1.60
1.40
1.50
1.60
(1)
VREF
VTT
VIH
-
0.90
-
VREF
VTT
VIH
-
0.90
-
-
VCCO
-
-
VCCO
-
VREF + 0.1
-
-
-
-
-
-
-
VREF + 0.1
-
-
-
-
-
-
-
VIL
-
VREF – 0.1
VIL
-
VREF – 0.1
VOH
VOL
VCCO – 0.4
-
0.4
-
VOH
VOL
VCCO – 0.4
-
0.4
-
-
-
I
OH at VOH (mA)
OL at VOL (mA)
–8
48
I
OH at VOH (mA)
OL at VOL (mA)
–8
24
I
-
I
-
Notes:
Notes:
1. Per EIA/JESD8-6, "The value of VREF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
1. Per EIA/JESD8-6, "The value of VREF is to be selected by the
user to provide optimum noise margin in the use conditions
specified by the user."
DS001-2 (v2.8) June 13, 2008
Product Specification
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