R
Spartan-II FPGA Family: Functional Description
the device configuration process until after the DLL
achieves lock.
Design Considerations
This section contains more detailed design information on
the following features:
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance
clocks.
•
•
•
Delay-Locked Loop . . . see page 27
Block RAM . . . see page 32
Versatile I/O . . . see page 36
Library DLL Primitives
Using Delay-Locked Loops
Figure 22 shows the simplified Xilinx library DLL macro,
BUFGDLL. This macro delivers a quick and efficient way to
provide a system clock with zero propagation delay
throughout the device. Figure 23 and Figure 24 show the
two library DLL primitives. These primitives provide access
to the complete set of DLL features when implementing
more complex applications.
The Spartan-II FPGA family provides up to four fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits that improve and
simplify system level design.
I
O
Introduction
0 ns
Quality on-chip clock distribution is important. Clock skew
and clock delay impact device performance and the task of
managing clock skew and clock delay with conventional
clock trees becomes more difficult in large devices. The
Spartan-II family of devices resolve this potential problem
by providing up to four fully digital dedicated on-chip
Delay-Locked Loop (DLL) circuits which provide zero
propagation delay and low clock skew between output clock
signals distributed throughout the device.
DS001_22_032300
Figure 22: Simplified DLL Macro BUFGDLL
CLKDLL
CLK0
CLKIN
CLKFB
CLK90
CLK180
CLK270
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network
minimizes clock skews due to loading differences. By
monitoring a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the
individual clock loads within the device.
CLK2X
CLKDV
LOCKED
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
RST
DS001_23_032300
Figure 23: Standard DLL Primitive CLKDLL
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at
100 MHz. This technique can simplify board design
because the clock path on the board no longer distributes
such a high-speed signal. A multiplied clock also provides
designers the option of time-domain-multiplexing, using one
circuit twice per clock cycle, consuming less area than two
copies of the same circuit.
CLKDLLHF
CLKIN
CLKFB
CLK0
CLK180
CLKDV
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to de-skew a board level clock between multiple devices.
RST
LOCKED
DS001_24_032300
In order to guarantee the system clock establishes prior to
the device "waking up," the DLL can delay the completion of
Figure 24: High-Frequency DLL Primitive CLKDLLHF
DS001-2 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
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