R
Spartan-II FPGA Family: Functional Description
CCLK
CS
T
T
SMCCCS
SMCSCC
T
WRITE
T
SMWCC
SMCCW
T
SMDCC
T
SMCCD
DATA[7:0]
BUSY
T
SMCKBY
No Write
Write
No Write
Write
DS001_20_061200
Symbol
Description
Units
TSMDCC
TSMCCD
TSMCSCC
TSMCCCS
TSMCCW
TSMWCC
TSMCKBY
FCC
D0-D7 setup/hold
D0-D7 hold
5
0
ns, min
ns, min
CS setup
7
ns, min
CS hold
0
ns, min
CCLK
WRITE setup
7
ns, min
WRITE hold
0
ns, min
BUSY propagation delay
Maximum frequency
Maximum frequency with no handshake
12
66
50
ns, max
MHz, max
MHz, max
FCCNH
Figure 20: Slave Parallel Write Timing
CCLK
CS
WRITE
DATA[7:0]
BUSY
Abort
DS001_21_032300
Figure 21: Slave Parallel Write Abort Waveforms
DS001-2 (v2.8) June 13, 2008
Product Specification
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Module 2 of 4
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