R
XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
Simple Timing Model
Figure 4
shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
PD
, t
SU
, and t
CO
. In other architectures, the user
may be able to fit the design into the CPLD, but is not sure
whether system timing requirements can be met until after
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sharable expand-
ers, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR3064A device, the user knows up front that if a
given output uses 5product terms or less, the t
PD
= 7.5 ns,
the t
SU_PAL
= 3.5 ns, and the t
CO
= 5.5 ns. If an output is
using six to 37 product terms, an additional 1.5 ns must be
added to the t
PD
and t
SU
timing parameters to account for
the time to propagate through the PLA array.
INPUT PIN
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
D
Q
REGISTERED
t
CO
OUTPUT PIN
GLOBAL CLOCK PIN
SP00441
Figure 4: CoolRunner Timing Model
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Figure 5
and
Table 1
showing the I
CC
vs.
Frequency of our XCR3064A TotalCMOS CPLD. (Data
taken with four up/down loadable 16-bit counters at 3.3V,
25
°
C)
5
www.xilinx.com
1-800-255-7778
DS037 (v1.1) February 10, 2000
XILINX [ XILINX, INC ]
