欢迎访问ic37.com |
会员登录 免费注册
发布采购

XCR3064A-12VQ100C 参数 Datasheet PDF下载

XCR3064A-12VQ100C图片预览
型号: XCR3064A-12VQ100C
PDF下载: 下载PDF文件 查看货源
内容描述: 64宏单元CPLD具有增强的时钟 [64 Macrocell CPLD With Enhanced Clocking]
分类和应用: 时钟
文件页数/大小: 18 页 / 550 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第1页浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第2页浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第3页浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第4页浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第6页浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第7页浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第8页浏览型号XCR3064A-12VQ100C的Datasheet PDF文件第9页  
R
XCR3064A: 64 Macrocell CPLD With Enhanced Clocking  
ers, varying number of X and Y routing channels used, etc.  
In the XPLA architecture, the user knows up front whether  
the design will meet system timing requirements. This is  
due to the simplicity of the timing model. For example, in  
the XCR3064A device, the user knows up front that if a  
Simple Timing Model  
Figure 4 shows the CoolRunner Timing Model. The Cool-  
Runner timing model looks very much like a 22V10 timing  
model in that there are three main timing parameters,  
including t , t , and t . In other architectures, the user  
PD SU  
CO  
given output uses 5product terms or less, the t = 7.5 ns,  
PD  
may be able to fit the design into the CPLD, but is not sure  
whether system timing requirements can be met until after  
the design has been fit into the device. This is because the  
timing models of competing architectures are very complex  
and include such things as timing dependencies on the  
number of parallel expanders borrowed, sharable expand-  
the t  
= 3.5 ns, and the t = 5.5 ns. If an output is  
SU_PAL  
CO  
using six to 37 product terms, an additional 1.5 ns must be  
added to the t and t timing parameters to account for  
PD  
SU  
the time to propagate through the PLA array.  
t
= COMBINATORIAL PAL ONLY  
= COMBINATORIAL PAL + PLA  
PD_PAL  
t
PD_PLA  
INPUT PIN  
OUTPUT PIN  
REGISTERED  
= PAL ONLY  
t
t
REGISTERED  
SU_PAL  
= PAL + PLA  
t
SU_PLA  
CO  
INPUT PIN  
D
Q
OUTPUT PIN  
SP00441  
GLOBAL CLOCK PIN  
Figure 4: CoolRunner Timing Model  
both high performance and low power, breaking the para-  
digm that to have low power, you must have low perfor-  
TotalCMOS Design Technique for Fast Zero  
Power  
mance. Refer to Figure 5 and Table 1 showing the I vs.  
CC  
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-  
cess technology and design technique. Xilinx employs a  
cascade of CMOS gates to implement its Sum of Products  
instead of the traditional sense amp approach. This CMOS  
gate implementation allows Xilinx to offer CPLDs which are  
Frequency of our XCR3064A TotalCMOS CPLD. (Data  
taken with four up/down loadable 16-bit counters at 3.3V,  
25°C)  
5
www.xilinx.com  
DS037 (v1.1) February 10, 2000  
1-800-255-7778  
 复制成功!