R
XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
The XCR3064A CPLD is reprogrammable using industry
standard device programmers from vendors such as Data
I/O, BPMicrosystems, SMS, and others. The XCR3064A
also includes an industry-standard, IEEE 1149.1, JTAG
interface through which In-System Programming (ISP) and
reprogramming of the device are supported.
16 macrocells. The six control terms can individually be
configured as either SUM or PRODUCT terms, and are
used to control the preset/reset and output enables of the
16 macrocells' flip-flops. In addition, two of the control
terms can be used as clock signals (see Macrocell Archi-
tecture Section for details). The PAL array consists of a pro-
grammable AND array with a fixed OR array, while the PLA
array consists of a programmable AND array with a pro-
grammable OR array. The PAL array provides a high speed
path through the array, while the PLA array provides
increased product term density.
XPLA Architecture
Figure 1 shows a high level block diagram of a 64 macrocell
device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
Each macrocell has five dedicated product terms from the
PAL array. The pin-to-pin t
of the XCR3064A device
PD
through the PAL array is 7.5 ns. If a macrocell needs more
than five product terms, it simply gets the additional product
terms from the PLA array. The PLA array consists of 32
product terms, which are available for use by all 16 macro-
cells. The additional propagation delay incurred by a mac-
rocell using one or all 32 PLA product terms is just 1.5 ns.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner™
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
So the total pin-to-pin t for the XCR3064A using six to 37
PD
product terms is 9.0 ns (7.5 ns for the PAL + 1.5 ns for the
PLA).
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic
block contains control terms, a PAL array, a PLA array, and
MC0
MC0
MC1
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
I/O
MC15
MC15
16
16
16
16
ZIA
MC0
MC1
MC0
MC1
36
36
LOGIC
BLOCK
LOGIC
BLOCK
I/O
I/O
MC15
MC15
16
16
16
16
SP00439
Figure 1: Xilinx XPLA CPLD Architecture
DS037 (v1.1) February 10, 2000
www.xilinx.com
2
1-800-255-7778
XILINX [ XILINX, INC ]
