R
Platform Flash In-System Programmable Configuration PROMS
(2)
V
CCO
(5)
External
Oscillator
(1)
V
V
V
CCO CCINT
CCJ
(3)
I/O
(1)
V
V
V
D[0:7]
D[0:7]
MODE PINS
RDWR_B
CS_B
CCINT
(2)
(3)
I/O
CCO
(2)
CCJ
1KΩ
1KΩ
XCFxxP
Xilinx FPGA
Platform Flash
PROM
Slave SelectMAP
(5)
CLK
CCLK
DONE
CE
CEO
D[0:7]
CCLK
...OPTIONAL
Slave FPGAs
with identical
configurations
OE/RESET
INIT_B
DONE
(6)
TDI
TDI
CF
PROG_B
INIT_B
PROG_B
(4)
(4)
TMS
TCK
TDO
TMS
TCK
BUSY
BUSY
(4)
BUSY
TDO
TDI
GND
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for
high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 If the XCFxxP Platform Flash PROM is not used with CLKOUT enabled to drive CCLK, then an external clock is required
for Slave SelectMAP (or Slave Parallel) modes. If CLKOUT is used, then it must be tied to a 4.7KΩ resistor pulled up
to V
.
CCO
6 For the XCFxxP the CF pin is a bidirectional pin.
ds123_15_031804
Figure 12: Configuring in Slave SelectMAP Mode
DS123 (v2.4) July 20, 2004
www.xilinx.com
18
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
