R
Platform Flash In-System Programmable Configuration PROMS
(2)
V
CCJ
V
CCO
V
CCINT
V
CCJ
V
CCO
V
CCINT
V
CCO
(1)
(1)
(1)
V
V
V
D[0:7]
D[0:7]
MODE PINS
D[0:7]
MODE PINS
V
V
V
D[0:7]
CCINT
(2)
CCINT
(2)
(3)
(3)
(3)
(3)
I/O
I/O
I/O
I/O
CCO
CCO
(2)
(2)
RDWR_B
CS_B
RDWR_B
CS_B
CCJ
CCJ
XCFxxP
XCFxxP
Platform Flash
PROM
Platform Flash
PROM
Xilinx FPGA
Master SelectMAP
Xilinx FPGA
Slave SelectMAP
First
PROM
(PROM 0)
CLK
CCLK
DONE
CCLK
DONE
CLK
Cascaded
PROM
(PROM 1)
CE
CE
CEO
CEO
OE/RESET
INIT_B
INIT_B
OE/RESET
(5)
(5)
TDI
TMS
TCK
TDO
CF
PROG_B
PROG_B
TDI
CF
(4)
(4)
(4)
(4)
BUSY
BUSY
BUSY
TMS
TCK
BUSY
TDI
TDO
TMS
TCK
GND
TDO
TDO
TDI
TDI
TMS
TCK
TMS
GND
TCK
TDO
GND
GND
Notes:
1
2
3
4
For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
For compatible voltages, refer to the appropriate data sheet.
CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for
high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
For the XCFxxP the CF pin is a bidirectional pin.
ds123_16_031804
5
Figure 13: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
DS123 (v2.4) July 20, 2004
www.xilinx.com
19
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
