R
Platform Flash In-System Programmable Configuration PROMS
Configuration PROM to FPGA Device Interface Connection Diagrams
(2)
V
CCO
(1)
V
V
V
CCO CCINT
CCJ
(1)
V
V
V
D0
DIN
MODE PINS
CCINT
(2)
CCO
(2)
DIN
CCLK
CCJ
...OPTIONAL
Slave FPGAs
with identical
configurations
Xilinx FPGA
Master Serial
Platform Flash
PROM
DONE
INIT_B
PROG_B
CLK
CE
CCLK
DONE
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
CEO
DOUT
DIN
CCLK
OE/RESET
INIT_B
(3)
TDI
TDI
CF
PROG_B
DONE
TMS
TCK
TDO
TMS
TCK
INIT_B
PROG_B
TDO
TDI
GND
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
ds123_11_071304
Figure 8: Configuring in Master Serial Mode
DS123 (v2.4) July 20, 2004
www.xilinx.com
14
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
