R
Platform Flash In-System Programmable Configuration PROMS
(2)
V
V
V
V
V
V
V
CCO
CCJ
CCO
CCINT
CCJ
CCO
CCINT
(1)
(1)
(1)
V
V
V
D0
DIN
MODE PINS
DOUT
MODE PINS
V
V
V
D0
CCINT
(2)
CCINT
(2)
DIN
CCO
(2)
CCO
(2)
CCJ
CCJ
Platform Flash
PROM
Xilinx FPGA
Master Serial
Xilinx FPGA
Slave Serial
Platform Flash
PROM
First
PROM
(PROM 0)
Cascaded
PROM
(PROM 1)
CLK
CE
CCLK
DONE
CCLK
DONE
CLK
CE
CEO
CEO
OE/RESET
INIT_B
INIT_B
OE/RESET
(3)
(3)
TDI
TMS
TCK
TDO
CF
PROG_B
PROG_B
TDI
CF
TMS
TCK
TDI
TDO
TMS
TCK
TDO
TDI
TDO
TDI
TMS
TCK
TMS
TCK
GND
GND
TDO
GND
GND
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
ds123_13_031804
Figure 10: Configuring Multiple Devices Master/Slave Serial Mode
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
16
XILINX [ XILINX, INC ]
