R
Platform Flash In-System Programmable Configuration PROMS
(2)
V
CCO
(3)
External
Oscillator
(1)
V
V
V
CCJ CCO CCINT
(1)
V
V
V
D0
DIN
MODE PINS
CCINT
(2)
CCO
(2)
DIN
CCLK
CCJ
...OPTIONAL
Slave FPGAs
with identical
configurations
Xilinx FPGA
Slave Serial
Platform Flash
PROM
DONE
INIT_B
PROG_B
(3)
CLK
CCLK
DONE
CE
CEO
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
DOUT
DIN
CCLK
OE/RESET
INIT_B
(4)
TDI
TMS
TCK
TDO
TDI
CF
PROG_B
DONE
TMS
TCK
INIT_B
PROG_B
TDO
TDI
GND
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or
optionally—for the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive
the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then it
must be tied to a 4.7KΩ resistor pulled up to V
4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin.
.
CCO
ds123_12_071304
Figure 9: Configuring in Slave Serial Mode
DS123 (v2.4) July 20, 2004
www.xilinx.com
15
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
