R
Platform Flash In-System Programmable Configuration PROMS
(2)
V
V
V
V
V
V
V
CCO
CCJ
CCO
CCINT
CCJ
CCO
CCINT
(3)
External
Oscillator
(1)
(1)
(1)
MODE PINS
DOUT
D0
V
V
V
D0
DIN
MODE PINS
V
V
V
CCINT
(2)
CCINT
(2)
DIN
CCO
(2)
CCO
(2)
CCJ
CCJ
XCFxxP
XCFxxP
Platform Flash
PROM
Platform Flash
PROM
Xilinx FPGA
Slave Serial
Xilinx FPGA
Slave Serial
(3)
(3)
CLK
CLK
CCLK
DONE
CCLK
DONE
First
PROM
(PROM 0)
Cascaded
PROM
(PROM 1)
CE
CE
CEO
CEO
OE/RESET
OE/RESET
INIT_B
INIT_B
(4)
(4)
TDI
TMS
TCK
TDO
CF
CF
PROG_B
PROG_B
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TDI
TMS
TCK
TMS
TCK
EN_EX_SEL
TDO
EN_EX_SEL
REV_SEL[1:0]
GND
REV_SEL[1:0]
GND
GND
GND
EN_EXT_SEL
REV_SEL[1:0]
DONE
Design
Revision
Control
Logic
CF / PROG_B
2
3
For compatible voltages, refer to the appropriate data sheet.
In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or
optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK).
If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled
up to V
.
CCO
For the XCFxxP the CF pin is a bidirectional pin.
4
ds123_17_031804
Figure 14: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
DS123 (v2.4) July 20, 2004
www.xilinx.com
20
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
