R
Platform Flash In-System Programmable Configuration PROMS
(2)
V
CCJ
V
V
V
CCJ
V
V
V
CCO
CCO CCINT
CCO CCINT
(5)
External
Oscillator
(1)
(1)
(1)
VCCINT
(2)
V
D[0:7]
D[0:7]
D[0:7]
MODE PINS
D[0:7]
MODE PINS
CCINT
(2)
V
V
V
RDWR_B
CS_B
RDWR_B
CS_B
CCO
CCO
(3)
I/O
(3)
I/O
(2)
(2)
V
CCJ
CCJ
XCFxxP
Platform Flash
PROM
XCFxxP
Platform Flash
PROM
Xilinx FPGA
Slave SelectMAP
Xilinx FPGA
Slave SelectMAP
(5)
(5)
First
PROM
(PROM 0)
Cascaded
PROM
(PROM 1)
CLK
CE
CEO
CLK
CCLK
DONE
CCLK
DONE
CE
CEO
OE/RESET
OE/RESET
INIT_B
INIT_B
(6)
(6)
TDI
TDI
CF
CF
PROG_B
PROG_B
(4)
(4)
(4)
(4)
TMS
TCK
TDO
TMS
TCK
BUSY
BUSY
BUSY
BUSY
TDI
TDO
TMS
TCK
TDO
TDI
TDO
TDI
TMS
TCK
TMS
EN_EX_SEL
EN_EX_SEL
TCK
TDO
REV_SEL[1:0]
REV_SEL[1:0]
GND
GND
GND
GND
EN_EXT_SEL
REV_SEL[1:0]
CF
Design
Revision
Control
Logic
DONE
PROG_B
CS_B[1:0]
Notes:
1
2
3
4
For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
For compatible voltages, refer to the appropriate data sheet.
RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only
required for high frequency SelectMAP mode configuration. For BUSY pin requirements, refer to
the appropriate FPGA data sheet.
5
In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or
optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK).
If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7KΩ resistor pulled
up to V
.
CCO
6
For the XCFxxP the CF pin is a bidirectional pin.
ds123_18_031804
Figure 15: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
DS123 (v2.4) July 20, 2004
www.xilinx.com
21
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
