R
Platform Flash In-System Programmable Configuration PROMS
Reset and Power-On Reset Activation
At power up, the device requires the V
power supply to
power-down threshold (V
), the PROM resets and
CCINT
CCPD
monotonically rise to the nominal operating voltage within
the specified V rise time. If the power supply cannot
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM. Once the required
supplies have reached their respective POR (Power On
OE/RESET is again held Low until the after the POR thresh-
old is reached. OE/RESET polarity is not programmable.
These power-up requirements are shown graphically in
Figure 16.
CCINT
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is deas-
serted (High). The address counter is reset, CEO is driven
High, and the remaining outputs are placed in a high-imped-
ance state.
Reset) thresholds, the OE/RESET release is delayed (T
OER
minimum) to allow more margin for the power supplies to
stabilize before initiating configuration. The OE/RESET pin
is connected to an external 4.7kΩ pull-up resistor and also
to the target FPGA's INIT pin. For systems utilizing slow-ris-
ing power supplies, an additional power monitoring circuit
can be used to delay the target configuration until the sys-
tem power reaches minimum operating voltages by holding
the OE/RESET pin Low. When OE/RESET is released, the
FPGA’s INIT pin is pulled High allowing the FPGA's config-
uration sequence to begin. If the power drops below the
Notes:
1. The XCFxxS PROM only requires V
to rise above
CCINT
its POR threshold before releasing OE/RESET.
2. The XCFxxP PROM requires both V to rise above
CCINT
its POR threshold and for V
to reach the
CCO
recommended operating voltage level before releasing
OE/RESET.
VCCINT
Recommended Operating Range
Delay or Restart
Configuration
50 ms ramp
200 µs ramp
VCCPOR
VCCPD
A slow-ramping V
supply may still
CCINT
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
V
and V
have reached their
CCINT
CCO
TIME (ms)
recommended operating conditions.
TOER
TOER
TRST
ds123_21_103103
Figure 16: Platform Flash PROM Power-Up Requirements
I/O Input Voltage Tolerance and Power
Sequencing
The I/Os on each re-programmable Platform Flash PROM
are fully 3.3V-tolerant. This allows 3V CMOS signals to con-
nect directly to the inputs without damage. The core power
Standby Mode
The PROM enters a low-power standby mode whenever CE
is deasserted (High). In standby mode, the address counter
is reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of
the OE/RESET input. For the device to remain in the
low-power standby mode, the JTAG pins TMS, TDI, and
TDO must not be pulled Low, and TCK must be stopped
(High or Low).
supply (V
), JTAG pin power supply (V
), output
CCINT
CCJ
power supply (V
), and external 3V CMOS I/O signals
CCO
can be applied in any order.
Additionally, for the XCFxxS PROM only, when V
is sup-
CCO
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
plied at 2.5V or 3.3V and V
is supplied at 3.3V, the I/Os
CCINT
are 5V-tolerant. This allows 5V CMOS signals to connect
directly to the inputs on a powered XCFxxS PROM without
damage. Failure to power the PROM correctly while supply-
ing a 5V input signal may result in damage to the XCFxxS
device.
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
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22
XILINX [ XILINX, INC ]
