XC7A50T-2CSG325C 参数 Datasheet PDF下载

型号：	XC7A50T-2CSG325C
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 4075 CLBs, 1286MHz, 52160-Cell, CMOS, PBGA325, BGA-325]
分类和应用：	时钟栅可编程逻辑
文件页数/大小：	64 页 / 1094 K
品牌：	XILINX [ XILINX, INC ]

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第25页

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第26页

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第27页

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第28页

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第30页

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第31页

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第32页

浏览型号XC7A50T-2CSG325C的Datasheet PDF文件第33页

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics

CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 28: CLB Distributed RAM Switching Characteristics

Speed Grade

Symbol

Description

1.0V

-2/-2LE

0.95V

-1LI

0.9V

-2LE

Units

-3

-1

-1Q/-1M

Sequential Delays

T_SHCKO

Clock to A – B outputs

0.98

1.37

1.09

1.53

1.32

1.86

1.32

1.86

1.32

1.86

1.54

2.18

ns, Max

T_{SHCKO_1}

Clock to AMUX – BMUX outputs

Setup and Hold Times Before/After Clock CLK

T_{DS_LRAM}

A – D inputs to CLK

0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 0.72/0.35 0.96/0.40 ns, Min

T_{DH_LRAM}

T_{AS_LRAM}

Address An inputs to clock

0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 0.37/0.70 0.43/0.71 ns, Min

0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 0.94/0.26 1.11/0.31 ns, Min

T_{AH_LRAM}

Address An inputs through MUXs

and/or carry logic to clock

T_{WS_LRAM}

WE input to clock

0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 0.53/0.17 0.62/0.13 ns, Min

0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 0.53/0.17 0.63/0.12 ns, Min

T_{WH_LRAM}

T_{CECK_LRAM}

T_{CKCE_LRAM}

CE input to CLK

Clock CLK

T_{MPW_LRAM}

T_MCP

Minimum pulse width

Minimum clock period

1.05

2.10

1.13

2.26

1.25

2.50

1.25

2.50

1.25

2.50

1.61

3.21

ns, Min

Notes:

also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.

SHCKO

CLB Shift Register Switching Characteristics (SLICEM Only)

Table 29: CLB Shift Register Switching Characteristics

Speed Grade

Symbol

Description

1.0V

-2/-2LE

0.95V

-1LI

0.9V

-2LE

Units

-3

-1

-1Q/-1M

Sequential Delays

T_REG

Clock to A – D outputs

1.19

1.58

1.12

1.33

1.77

1.23

1.61

2.15

1.46

1.61

2.15

1.46

1.61

2.15

1.46

1.89

2.53

1.68

ns, Max

T_{REG_MUX}

T_{REG_M31}

Clock to AMUX – DMUX output

Clock to DMUX output via M31

output

Setup and Hold Times Before/After Clock CLK

0.37/0.10 0.41/0.12 0.51/0.17 0.51/0.17 0.51/0.17

0.37/0.10 0.42/0.11 0.52/0.17 0.52/0.17 0.52/0.17

0.33/0.34 0.37/0.37 0.44/0.43 0.44/0.44 0.44/0.43

T_{WS_SHFREG}

WE input

0.59/0.13 ns, Min

0.60/0.12 ns, Min

0.54/0.55 ns, Min

T_{WH_SHFREG}

T_{CECK_SHFREG}

T_{CKCE_SHFREG}

CE input to CLK

A – D inputs to CLK

T_{DS_SHFREG}

T_{DH_SHFREG}

Clock CLK

T_{MPW_SHFREG}

Minimum pulse width

0.77

0.86

0.98

1.22

ns, Min

DS181 (v1.25) June 18, 2018

www.xilinx.com

Product Specification

电子百科

产品导航

XC7A50T-2CSG325C 参数 Datasheet PDF下载

IC37:专业IC行业平台