Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Input/Output Delay Switching Characteristics
Table 25: Input/Output Delay Switching Characteristics
Speed Grade
Symbol
Description
1.0V
-2/-2LE
0.95V
-1LI
0.9V
-2LE
Units
-3
-1
-1Q/-1M
IDELAYCTRL
TDLYCCO_RDY
FIDELAYCTRL_REF
Reset to ready for IDELAYCTRL
3.67
3.67
3.67
3.67
3.67
3.67
µs
Attribute REFCLK
200.00
200.00
200.00
200.00
200.00
200.00
MHz
frequency = 200.00(1)
Attribute REFCLK
300.00
400.00
300.00
400.00
300.00
N/A
300.00
N/A
300.00
N/A
300.00
N/A
MHz
MHz
frequency = 300.00(1)
Attribute REFCLK
frequency = 400.00(1)
IDELAYCTRL_REF_
PRECISION
REFCLK precision
10
10
10
10
10
10
MHz
ns
TIDELAYCTRL_RPW
IDELAY
Minimum Reset pulse width
59.28
59.28
59.28
59.28
59.28
59.28
TIDELAYRESOLUTION
IDELAY chain delay resolution
1/(32 x 2 x FREF
)
µs
Pattern dependent period jitter in
delay chain for clock pattern.(2)
0
5
0
5
0
0
0
5
0
5
ps
per tap
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)(3)
5
5
ps
per tap
TIDELAYPAT_JIT
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)(4)
9
9
9
9
9
9
ps
per tap
TIDELAY_CLK_MAX
Maximum frequency of CLK input
to IDELAY
680.00
680.00
600.00
600.00
600.00
520.00
MHz
ns
TIDCCK_CE
TIDCKC_CE
/
CE pin setup/hold with respect to 0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 0.21/0.16 0.14/0.16
C for IDELAY
TIDCCK_INC
TIDCKC_INC
/
INC pin setup/hold with respect to 0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 0.16/0.22 0.10/0.23
C for IDELAY
ns
TIDCCK_RST
/
RST pin setup/hold with respect 0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 0.18/0.14 0.22/0.19
to C for IDELAY
ns
TIDCKC_RST
TIDDO_IDATAIN
Propagation delay through
IDELAY
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.
DS181 (v1.25) June 18, 2018
www.xilinx.com
Product Specification
26