Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 20: Output Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12
(1)
RREF CREF
VMEAS VREF
(Ω)
50
50
25
50
25
50
50
50
50
50
(pF)
(V)
(V)
0
0
0
0
0
0
0
0
0
0
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0.6
HSTL, Class I, 1.5V
HSTL_I
0.75
0.75
0.9
HSTL, Class II, 1.5V
HSTL_II
HSTL, Class I, 1.8V
HSTL_I_18
HSTL, Class II, 1.8V
HSTL_II_18
0.9
HSUL (High-Speed Unterminated Logic), 1.2V
SSTL12, 1.2V
HSUL_12
0.6
SSTL12
0.6
SSTL135/SSTL135_R, 1.35V
SSTL15/SSTL15_R, 1.5V
SSTL135, SSTL135_R
SSTL15, SSTL15_R
SSTL18_I, SSTL18_II
0.675
0.75
0.9
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
DIFF_MOBILE_DDR, 1.8V
DIFF_HSTL, Class I, 1.2V
DIFF_HSTL, Class I & II, 1.5V
DIFF_HSTL, Class I & II, 1.8V
DIFF_HSUL_12, 1.2V
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V
DIFF_SSTL18, Class I & II, 1.8V
LVDS, 2.5V
DIFF_MOBILE_DDR
DIFF_HSTL_I_12
50
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0(2)
0.9
0.6
0.75
0.9
0.6
0.675
0.75
0.9
0
DIFF_HSTL_I, DIFF_HSTL_II
DIFF_HSTL_I_18, DIFF_HSTL_II_18
DIFF_HSUL_12
50
50
50
DIFF_SSTL135, DIFF_SSTL135_R
DIFF_SSTL15, DIFF_SSTL15_R
DIFF_SSTL18_I, DIFF_SSTL18_II
LVDS_25
50
50
50
100
100
100
100
100
50
BLVDS (Bus LVDS), 2.5V
Mini LVDS, 2.5V
BLVDS_25
0(2)
0
MINI_LVDS_25
0(2)
0
PPDS_25
PPDS_25
0(2)
0
RSDS_25
RSDS_25
0(2)
0
TMDS_33
TMDS_33
0(2)
3.3
Notes:
1.
C
is the capacitance of the probe, nominally 0 pF.
REF
2. The value given is the differential output voltage.
DS181 (v1.25) June 18, 2018
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Product Specification
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