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XC6VLX75T-1FFG484C 参数 Datasheet PDF下载

XC6VLX75T-1FFG484C图片预览
型号: XC6VLX75T-1FFG484C
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1098MHz, 74496-Cell, CMOS, PBGA484, 23 X 23 MM, LEAD FREE, FBGA-484]
分类和应用: 时钟可编程逻辑
文件页数/大小: 65 页 / 1429 K
品牌: XILINX [ XILINX, INC ]
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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics  
Table 23: GTX Transceiver Transmitter Switching Characteristics  
Symbol  
Description  
Serial data rate range  
Condition  
Min  
Typ  
Max  
FGTXMAX  
Units  
Gb/s  
ps  
ps  
ps  
mV  
ns  
UI  
FGTXTX  
TRTX  
0.480  
TX Rise time  
20%–80%  
80%–20%  
120  
120  
TFTX  
TX Fall time  
TLLSKEW  
TX lane-to-lane skew(1)  
Electrical idle amplitude  
Electrical idle transition time  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
350  
15  
VTXOOBVDPP  
TTXOOBTRANSITION  
TJ6.5  
75  
0.33  
0.17  
0.33  
0.15  
0.33  
0.14  
0.34  
0.16  
0.2  
6.5 Gb/s  
5.0 Gb/s  
DJ6.5  
UI  
TJ5.0  
UI  
DJ5.0  
UI  
TJ4.25  
UI  
4.25 Gb/s  
3.75 Gb/s  
3.125 Gb/s  
3.125 Gb/s(4)  
2.5 Gb/s(5)  
1.25 Gb/s(6)  
600 Mb/s  
DJ4.25  
UI  
TJ3.75  
UI  
DJ3.75  
UI  
TJ3.125  
DJ3.125  
TJ3.125L  
DJ3.125L  
TJ2.5  
UI  
0.1  
UI  
0.35  
0.16  
0.20  
0.08  
0.15  
0.06  
0.1  
UI  
UI  
UI  
DJ2.5  
UI  
TJ1.25  
UI  
DJ1.25  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
Deterministic Jitter(2)(3)  
Total Jitter(2)(3)  
UI  
TJ600  
UI  
DJ600  
0.03  
0.1  
UI  
TJ480  
UI  
480 Mb/s  
DJ480  
Deterministic Jitter(2)(3)  
0.03  
UI  
Notes:  
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).  
2. Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.  
-12  
3. All jitter values are based on a bit-error ratio of 1e  
4. PLL frequency at 1.5625 GHz and OUTDIV = 1.  
5. PLL frequency at 2.5 GHz and OUTDIV = 2.  
6. PLL frequency at 2.5 GHz and OUTDIV = 4.  
.
DS152 (v3.6) March 18, 2014  
www.xilinx.com  
Product Specification  
15  
 
 
 
 
 
 
 
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