Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 24: GTX Transceiver Receiver Switching Characteristics
Symbol Description
RX oversampler not enabled
RX oversampler enabled
Min
0.600
0.480
–
Typ
–
Max
FGTXMAX
0.600
–
Units
Gb/s
Gb/s
ns
FGTXRX
Serial data rate
–
TRXELECIDLE
RXOOBVDPP
Time for RXELECIDLE to respond to loss or restoration of data
OOB detect threshold peak-to-peak
75
–
60
150
mV
Receiver spread-spectrum
Modulated @ 33 KHz
tracking(1)
–5000
–
0
ppm
RXSST
RXRL
Run length (CID)
Internal AC capacitor bypassed
CDR 2nd-order loop disabled
CDR 2nd-order loop enabled
–
–
–
–
512
200
UI
–200
–2000
ppm
ppm
Data/REFCLK PPM offset
tolerance
RXPPMTOL
2000
SJ Jitter Tolerance(2)
JT_SJ6.5
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
6.5 Gb/s
0.44
0.44
0.44
0.44
0.45
0.45
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
JT_SJ5.0
5.0 Gb/s
JT_SJ4.25
4.25 Gb/s
3.75 Gb/s
3.125 Gb/s
3.125 Gb/s(4)
2.5 Gb/s(5)
1.25 Gb/s(6)
600 Mb/s
JT_SJ3.75
JT_SJ3.125
JT_SJ3.125L
JT_SJ2.5
JT_SJ1.25
0.5
JT_SJ600
0.4
JT_SJ480
480 Mb/s
0.4
SJ Jitter Tolerance with Stressed Eye(2)
3.125 Gb/s
5.0 Gb/s
0.70
0.70
0.1
–
–
–
–
–
–
–
–
UI
UI
UI
UI
JT_TJSE3.125
Total Jitter with Stressed Eye(7)
3.125 Gb/s
5.0 Gb/s
Sinusoidal Jitter with Stressed
Eye(7)
JT_SJSE3.125
0.1
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 1e
–12
.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. PLL frequency at 1.5625 GHz and OUTDIV = 1.
5. PLL frequency at 2.5 GHz and OUTDIV = 2.
6. PLL frequency at 2.5 GHz and OUTDIV = 4.
7. Composite jitter with RX equalizer enabled. DFE disabled.
DS152 (v3.6) March 18, 2014
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Product Specification
16
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