Spartan-3E FPGA Family: Functional Description
The connections for the bottom-edge BUFGMUX elements
are similar to the top-edge connections (see Figure 46).
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
X-Ref Target - Figure 46
Left-/Right-Half BUFGMUX
CLK Switch
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
Matrix
BUFGMUX
BUFGMUX
O
S
S
I0
I0
0
1
0
1
O
O
I1
I1
I0
I1
I0
I1
0
1
0
1
O
S
S
LHCLK or
RHCLK input
1st GCLK pin
1st DCM output
Double Line
Double Line
DCM output*
*(XC3S1200E and
XC3S1600E only)
2nd DCM output
2nd GCLK pin
DS312-2_16_110706
Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity
Quadrant Clock Routing
Table 42: QFP Package Clock Quadrant Locations
Clock Pins
GCLK[3:0]
Quadrant
BR
The clock routing within the FPGA is quadrant-based, as
shown in Figure 45. Each clock quadrant supports eight
total clock signals, labeled ‘A’ through ‘H’ in Table 41 and
Figure 47. The clock source for an individual clock line
originates either from a global BUFGMUX element along
the top and bottom edges or from a BUFGMUX element
along the associated edge, as shown in Figure 47. The
clock lines feed the synchronous resource elements (CLBs,
IOBs, block RAM, multipliers, and DCMs) within the
quadrant.
GCLK[7:4]
TR
GCLK[11:8]
GCLK[15:12]
RHCLK[3:0]
RHCLK[7:4]
LHCLK[3:0]
LHCLK[7:4]
TL
BL
BR
TR
TL
BL
The four quadrants of the device are:
•
•
•
•
Top Right (TR)
Bottom Right (BR)
Bottom Left (BL)
Top Left (TL)
In a few cases, a dedicated input is physically in one
quadrant of the device but connects to a different clock
quadrant:
•
•
•
FT256, H16 is in clock quadrant BR
FG320, K2 is in clock quadrant BL
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement
constraints.
FG400, L8 is in clock quadrant TL and the I/O at N11 is
in clock quadrant BL
•
FG484, M2 is in clock quadrant TL and L15 is in clock
quadrant BR
To estimate the quadrant location for a particular I/O, see
the footprint diagrams in Module 4, Pinout Descriptions. For
exact quadrant locations, use the floorplanning tool. In the
QFP packages (VQ100, TQ144 and PQ208) the quadrant
borders fall in the middle of each side of the package, at a
GND pin. The clock inputs fall on the quadrant boundaries,
as indicated in Table 42.
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
