Spartan-3E FPGA Family: Functional Description
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following sources:
two GCLK pins, two DCM outputs, or one Double-Line
interconnect.
The four BUFGMUX elements on the top edge are paired
together and share inputs from the eight global clock inputs
along the top edge. Each BUFGMUX pair connects to four
of the eight global clock inputs, as shown in Figure 45. This
optionally allows differential inputs to the global clock inputs
without wasting a BUFGMUX element.
Table 41 indicates permissible connections between clock
inputs and BUFGMUX elements. The I0-input provides the
best input path to a clock buffer. The I1-input provides the
secondary input for the clock multiplexer function.
Table 41: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadran
t Clock
Line(1)
Left-Half BUFGMUX
Location(2) I0 Input
I1 Input
Top or Bottom BUFGMUX
Right-Half BUFGMUX
Location(2) I0 Input
I1 Input
(2)
Location
I0 Input
I1 Input
GCLK7 or
GCLK11
GCLK6 or
GCLK10
H
G
F
X0Y9
X0Y8
X0Y7
X0Y6
X0Y5
X0Y4
X0Y3
X0Y2
LHCLK7
LHCLK6
LHCLK5
LHCLK4
LHCLK3
LHCLK2
LHCLK1
LHCLK0
LHCLK6
LHCLK7
LHCLK4
LHCLK5
LHCLK2
LHCLK3
LHCLK0
LHCLK1
X1Y10
X1Y11
X2Y10
X2Y11
X1Y0
X3Y9
X3Y8
X3Y7
X3Y6
X3Y5
X3Y4
X3Y3
X3Y2
RHCLK3
RHCLK2
RHCLK1
RHCLK0
RHCLK7
RHCLK6
RHCLK5
RHCLK4
RHCLK2
RHCLK3
RHCLK0
RHCLK1
RHCLK6
RHCLK7
RHCLK4
RHCLK5
GCLK6 or
GCLK10
GCLK7 or
GCLK11
GCLK5 or
GCLK9
GCLK4 or
GCLK8
GCLK4 or
GCLK8
GCLK5 or
GCLK9
E
D
C
B
GCLK3 or
GCLK15
GCLK2 or
GCLK14
GCLK2 or
GCLK14
GCLK3 or
GCLK15
X1Y1
GCLK1 or
GCLK13
GCLK0 or
GCLK12
X2Y0
GCLK0 or
GCLK12
GCLK1 or
GCLK13
A
X2Y1
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 45 for specific BUFGMUX locations, and Figure 47 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
DS312 (v4.2) December 14, 2018
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Product Specification
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