Spartan-3E FPGA Family: Functional Description
Status Logic
The Status Logic indicates the present state of the DCM
and a means to reset the DCM to its initial known state. The
Status Logic signals are described in Table 37.
frequency. The RST signal must be asserted for three or
more CLKIN cycles. A DCM reset does not affect attribute
values (for example, CLKFX_MULTIPLY and
CLKFX_DIVIDE). If not used, RST is tied to GND.
In general, the Reset (RST) input is only asserted upon
configuring the FPGA or when changing the CLKIN
The eight bits of the STATUS bus are described in Table 38.
Table 37: Status Logic Signals
Signal
Direction
Input
Description
RST
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of
zero. Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0]
LOCKED
Output
Output
The bit values on the STATUS bus provide information regarding the state of DLL and PS
operation
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are
out-of-phase when Low.
Table 38: DCM Status Bus
Bit
0
Name
Reserved
Description
-
1
CLKIN Stopped
CLKFX Stopped
Reserved
When High, indicates that the CLKIN input signal is not toggling. When Low, indicates CLKIN is toggling.
This bit functions only when the CLKFB input is connected.(1)
2
When High, indicates that the CLKFX output is not toggling. When Low, indicates the CLKFX output is
toggling. This bit functions only when the CLKFX or CLKFX180 output are connected.
3-6
-
Notes:
1. When only the DFS clock outputs but none of the DLL clock outputs are used, this bit does not go High when the CLKIN signal stops.
Stabilizing DCM Clocks Before User Mode
Spread Spectrum
The STARTUP_WAIT attribute shown in Table 39 optionally
delays the end of the FPGA’s configuration process until
after the DCM locks to its incoming clock frequency. This
option ensures that the FPGA remains in the Startup phase
of configuration until all clock outputs generated by the
DCM are stable. When all DCMs that have their
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays for
details.
STARTUP_WAIT attribute set to TRUE assert the LOCKED
signal, then the FPGA completes its configuration process
and proceeds to user mode. The associated bitstream
generator (BitGen) option LCK_cycle specifies one of the
six cycles in the Startup phase. The selected cycle defines
the point at which configuration stalls until all the LOCKED
outputs go High. See Start-Up, page 106 for more
information.
Table 39: STARTUP_WAIT Attribute
Attribute
Description
Values
STARTUP_WAIT
When TRUE, delays TRUE, FALSE
transition from
configuration to user
mode until DCM
locks to the input
clock.
DS312 (v4.2) December 14, 2018
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Product Specification
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