Spartan-3E FPGA Family: Functional Description
Direct Connections
Direct connect lines route signals to neighboring tiles:
vertically, horizontally, and diagonally. These lines most
often drive a signal from a “source” tile to a double, hex, or
long line and conversely from the longer interconnect back
to a direct line accessing a “destination” tile.
Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in Table 43. These signals are available to the FPGA
application via the STARTUP_SPARTAN3E primitive.
Table 43: Spartan-3E Global Logic Control Signals
Global Control
Description
Input
Global Set/Reset: When High,
asynchronously places all registers and
flip-flops in their initial state (see Initialization,
page 32). Asserted automatically during the
GSR
FPGA configuration process (see Start-Up,
page 106).
Global Three-State: When High,
asynchronously forces all I/O pins to a
high-impedance state (Hi-Z, three-state).
GTS
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted
automatically during the FPGA configuration process,
guaranteeing that the FPGA starts-up in a known state.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for Dynamically Loading Multiple
Configuration Images Using MultiBoot Option, page 92. The
CLK input is an alternate clock for configuration Start-Up,
page 106.
DS312 (v4.2) December 14, 2018
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