Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 45
Global Clock Inputs
GCLK11 GCLK10
GCLK9 GCLK8
4
GCLK7 GCLK6
GCLK5
GCLK4 4
DCM
BUFGMUX
pair
DCM
Clock Line
XC3S100E (X0Y1)
XC3S250E (X1Y1)
XC3S500E (X1Y1)
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
XC3S250E (X0Y1)
XC3S500E (X0Y1)
XC3S1200E (X1Y3)
XC3S1600E (X1Y3)
X1Y10 X1Y11
X2Y10 X2Y11
in Quadrant
BUFGMUX
4
4
H
G
F
E
H
G
H
Top Right
Top Left
Quadrant (TR)
Quadrant (TL)
8
8
8
4
G
•
•
•
•
•
•
2
2
2
2
8
DCM
DCM
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
8
8
2
2
2
2
F
F
Note 3
Note 4
E
D
E
D
8
8
8
8
Left Spine
Right Spine
Horizontal
Spine
Note 3
Note 4
•
8
•
8
C
C
2
2
2
2
8
8
DCM
DCM
•
•
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
2
2
2
2
•
•
B
A
B
4
Bottom Right
Quadrant (BR)
8
8
Bottom Left
Quadrant (BL)
A
4
4
DCM
DCM
D
C
B
A
XC3S100E (X0Y0)
XC3S250E (X1Y0)
XC3S500E (X1Y0)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
XC3S250E (X0Y0)
XC3S500E (X0Y0)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
X1Y0 X1Y1
X2Y0 X2Y1
GCLK1 GCLK0
4
4 GCLK3
GCLK2
GCLK15 GCLK14 GCLK13 GCLK12
Global Clock Inputs
DS312-2_04_041106
Notes:
1. The diagram presents electrical connectivity. The diagram locations do not necessarily match the physical location on the
device, although the coordinate locations shown are correct.
2. Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the
XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die.
3. See Figure 47a, which shows how the eight clock lines are multiplexed on the left-hand side of the device.
4. See Figure 47b, which shows how the eight clock lines are multiplexed on the right-hand side of the device.
5. For best direct clock inputs to a particular clock buffer, not a DCM, see Table 41.
6. For best direct clock inputs to a particular DCM, not a BUFGMUX, see Table 30, Table 31, and Table 32. Direct pin inputs to a
DCM are shown in gray.
Figure 45: Spartan-3E Internal Quadrant-Based Clock Network (Electrical Connectivity View)
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
