Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 47
Clock Line
BUFGMUX Output
X1Y10 (Global)
Clock Line
BUFGMUX Output
X1Y10 (Global)
H
H
X0Y9 (Left Half)
X3Y9 (Right Half)
X1Y11 (Global)
X0Y8 (Left Half)
X1Y11 (Global)
G
F
G
F
X3Y8 (Right Half)
X2Y10 (Global)
X0Y7 (Left Half)
X2Y10 (Global)
X3Y7 (Right Half)
X2Y11 (Global)
X0Y6 (Left Half)
X2Y11 (Global)
E
D
C
B
E
D
C
B
X3Y6 (Right Half)
X1Y0 (Global)
X1Y0 (Global)
X0Y5 (Left Half)
X3Y5 (Right Half)
X1Y1 (Global)
X1Y1 (Global)
X0Y4 (Left Half)
X3Y4 (Right Half)
X2Y0 (Global)
X2Y0 (Global)
X0Y3 (Left Half)
X3Y3 (Right Half)
X2Y1 (Global)
X2Y1 (Global)
A
A
X0Y2 (Left Half)
X3Y2 (Right Half)
a. Left (TL and BL Quadrants) Half of Die
b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_103105
Figure 47: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements
connect to two vertical spines, each comprising four vertical
clock lines as shown in Figure 45. At the center of the die,
these clock signals connect to the eight-line horizontal clock
spine.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
in a single clock quadrant. Figure 47 shows how the clock
lines in each quadrant are selected from associated
BUFGMUX sources. For example, if quadrant clock ‘A’ in
the bottom left (BL) quadrant originates from
BUFGMUX_X2Y1, then the clock signal from
BUFGMUX_X0Y2 is unavailable in the bottom left quadrant.
However, the top left (TL) quadrant clock ‘A’ can still solely
use the output from either BUFGMUX_X2Y1 or
BUFGMUX_X0Y2 as the source.
To minimize the dynamic power dissipation of the clock
network, the Xilinx development software automatically
disables all clock segments not in use.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
62
XILINX [ XILINX, INC ]
