Spartan-3E FPGA Family: Functional Description
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
Interconnect
For additional information, refer to the “Using Interconnect”
chapter in UG331.
Switch Matrix
Interconnect is the programmable network of signal
pathways between the inputs and outputs of functional
elements within the FPGA, such as IOBs, CLBs, DCMs, and
block RAM.
The switch matrix connects to the different kinds of
interconnects across the device. An interconnect tile, shown
in Figure 48, is defined as a single switch matrix connected
to a functional element, such as a CLB, IOB, or DCM. If a
functional element spans across multiple switch matrices
such as the block RAM or multipliers, then an interconnect
tile is defined by the number of switch matrices connected
to that functional element. A Spartan-3E device can be
represented as an array of interconnect tiles where
interconnect resources are for the channel between any two
adjacent interconnect tile rows or columns as shown in
Figure 49.
Overview
Interconnect, also called routing, is segmented for optimal
connectivity. Functionally, interconnect resources are
identical to that of the Spartan-3 architecture. There are four
kinds of interconnects: long lines, hex lines, double lines,
and direct lines. The Xilinx Place and Route (PAR) software
X-Ref Target - Figure 48
Switch
Matrix
Switch
Matrix
CLB
IOB
Switch
Matrix
Switch
Matrix
18Kb
Block
RAM
MULT
18 x 18
Switch
Matrix
Switch
Matrix
DCM
Switch
Matrix
DS312_08_100110
Figure 48: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
X-Ref Target - Figure 49
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
IOB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
IOB
CLB
CLB
CLB
CLB
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
Switch
Matrix
DS312_09_100110
Figure 49: Array of Interconnect Tiles in Spartan-3E FPGA
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
63
XILINX [ XILINX, INC ]
