Spartan-3E FPGA Family: Functional Description
VARIABLE Phase Shift Mode
In VARIABLE phase shift mode, the FPGA application
dynamically adjusts the fine phase shift value using three
inputs to the PS unit (PSEN, PSCLK, and PSINCDEC), as
defined in Table 36 and shown in Figure 40.
Table 36: Signals for Variable Phase Mode
Signal
PSEN(1)
Direction
Input
Description
Enables the Phase Shift unit for variable phase adjustment.
PSCLK(1)
Input
Input
Clock to synchronize phase shift adjustment.
PSINCDEC(1)
When High, increments the current phase shift value. When Low, decrements the current
phase shift value. This signal is synchronized to the PSCLK signal.
PSDONE
Output
Goes High to indicate that the present phase adjustment is complete and PS unit is ready for
next phase adjustment request. This signal is synchronized to the PSCLK signal.
Notes:
1. This input supports either a true or inverted polarity.
The FPGA application uses the three PS inputs on the
Phase Shift unit to dynamically and incrementally increase
or decrease the phase shift amount on all nine DCM clock
outputs.
phase shift range measured in time and not steps, use
MAX_STEPS derived in Equation 6 and Equation 7 for
VALUE in Equation 4 and Equation 5.
If CLKIN < 60 MHz:
To adjust the current phase shift value, the PSEN enable
signal must be High to enable the PS unit. Coincidently,
PSINCDEC must be High to increment the current phase
shift amount or Low to decrement the current amount. All
VARIABLE phase shift operations are controlled by the
PSCLK input, which can be the CLKIN signal or any other
clock signal.
MAX_STEPS = [INTEGER(10 • (T
– 3))]
– 3))]
Eq 6
Eq 7
CLKIN
If CLKIN ≥ 60 MHz:
MAX_STEPS = [INTEGER(15 • (T
CLKIN
The phase adjustment might require as many as 100 CLKIN
cycles plus 3 PSCLK cycles to take effect, at which point the
DCM’s PSDONE output goes High for one PSCLK cycle.
This pulse indicates that the PS unit completed the previous
adjustment and is now ready for the next request.
Design Note
The VARIABLE phase shift feature operates differently from
the Spartan-3 DCM; use the DCM_SP primitive, not the
DCM primitive.
Asserting the Reset (RST) input returns the phase shift to
zero.
DCM_DELAY_STEP
DCM_DELAY_STEP is the finest delay resolution available
in the PS unit. Its value is provided at the bottom of
Table 105 in Module 3. For each enabled PSCLK cycle that
PSINCDEC is High, the PS unit adds one DCM_
DELAY_STEP of phase shift to all nine DCM outputs.
Similarly, for each enabled PSCLK cycle that PSINCDEC is
Low, the PS unit subtracts one DCM_ DELAY_STEP of
phase shift from all nine DCM outputs.
Because each DCM_DELAY_STEP has a minimum and
maximum value, the actual phase shift delay for the present
phase increment/decrement value (VALUE) falls within the
minimum and maximum values according to Equation 4 and
Equation 5.
T
T
(Max) = VALUE • DCM_DELAY_STEP_MAX Eq 4
PS
Eq 5
(Min) = VALUE • DCM_DELAY_STEP_MIN
PS
The maximum variable phase shift steps, MAX_STEPS, is
described in Equation 6 or Equation 7, for a given CLKIN
input period, T
, in nanoseconds. To convert this to a
CLKIN
DS312 (v4.2) December 14, 2018
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Product Specification
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