Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 29
initialized distributed RAM contents are not disturbed during
the configuration process.
SRLC16E
D
CE
CLK
A0
A1
A2
A3
Q
Q15
The distributed RAM is useful for smaller amounts of
memory. Larger memory requirements can use the
dedicated 18Kbit RAM blocks (see Block RAM).
Shift Registers
DS312-2_43_021305
For additional information, refer to the “Using Look-Up
Tables as Shift Registers (SRL16)” chapter in UG331.
Figure 29: SRL16 Shift Register Component with
Cascade and Clock Enable
It is possible to program each SLICEM LUT as a 16-bit shift
register (see Figure 28). Used in this way, each LUT can
delay serial data anywhere from 1 to 16 clock cycles without
using any of the dedicated flip-flops. The resulting
programmable delays can be used to balance the timing of
data pipelines.
The functionality of the shift register is shown in Table 20.
The SRL16 shifts on the rising edge of the clock input when
the Clock Enable control is High. This shift register cannot
be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
The SLICEM LUTs cascade from the G-LUT to the F-LUT
through the DIFMUX (see Figure 15). SHIFTIN and
SHIFTOUT lines cascade a SLICEM to the SLICEM below
to form larger shift registers. The four SLICEM LUTs of a
single CLB can be combined to produce delays up to 64
clock cycles. It is also possible to combine shift registers
across more than one CLB.
Table 20: SRL16 Shift Register Function
Inputs
Outputs
Am
Am
Am
CLK
CE
0
D
X
D
Q
Q15
Q[15]
Q[15]
X
Q[Am]
X-Ref Target - Figure 28
↑
1
Q[Am-1]
SRLC16
SHIFTIN
Notes:
1. m = 0, 1, 2, 3.
SHIFT-REG
4
Output
D
A[3:0]
A[3:0]
MC15
Registered
Output
D
Q
DI
WS
DI (BY)
(optional)
WSG
CE (SR)
CLK
WE
CK
SHIFTOUT
or YB
X465_03_040203
Figure 28: Logic Cell SRL16 Structure
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access
to any bit in the shift register through the normal D output.
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1]
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the
addressable bit.
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See
Figure 29 for an example of the SRLC16E component.
DS312 (v4.2) December 14, 2018
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Product Specification
34
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