Spartan-3E FPGA Family: Functional Description
Design Note
Block RAM Port Signal Definitions
Whenever a block RAM port is enabled (ENA or
ENB = High), all address transitions must meet the data
sheet setup and hold times with respect to the port clock
(CLKA or CLKB), as shown in Table 103, page 139.This
requirement must be met even if the RAM read output is of
no interest.
Representations of the dual-port primitive
RAMB16_S[w ]_S[w ] and the single-port primitive
A
B
RAMB16_S[w] with their associated signals are shown in
Figure 32a and Figure 32b, respectively. These signals are
defined in Table 23. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
X-Ref Target - Figure 32
RAMB16_SWA_SWB
WEA
ENA
SSRA
DOPA[pA–1:0]
CLKA
DOA[wA–pA–1:0]
ADDRA[rA–1:0]
DIA[wA–pA–1:0]
DIPA[pA–1:0]
RAMB16_Sw
WEB
ENB
WE
EN
SSRB
SSR
DOPB[pB–1:0]
DOP[p–1:0]
CLK
CLKB
DOB[wB–pB–1:0]
DO[w–p–1:0]
ADDRB[rB–1:0]
DIB[wB–pB–1:0]
DIPB[pB–1:0]
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
(a) Dual-Port
(b) Single-Port
DS312-2_03_111105
Notes:
1.
2.
3.
w and w are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
A B
p
and p are integers that indicate the number of data path lines serving as parity bits.
B
A
r
and r are integers representing the address bus width at ports A and B, respectively.
A
B
4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
Figure 32: Block RAM Primitives
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
