Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 31
Parity
Data
Address
35 34 33 32 31
P3 P2 P1 P0
24 23
16 15
8 7
0
0
Byte 3
Byte 2
Byte 1
Byte 0
512x36
0
17 16 15
P3 P2
8 7
Byte 3
Byte 1
Byte 2
Byte 0
1
0
1Kx18
P1 P0
8
7
0
P3
P2
P1
P0
Byte 3
Byte 2
Byte 1
Byte 0
3
2
1
0
2Kx9
3
2 1 0
7 6 5 4
3 2 1 0
7
6
4Kx4
7 6 5 4
3 2 1 0
1
0
1
0
7 6
5 4
3 2
1 0
F
E
D
C
8Kx2
7 6
5 4
3 2
1 0
3
2
1
0
0
7
6
5
4
1F
1E
1D
1C
16Kx1
3
2
1
0
3
2
1
0
DS312-2_02_102105
Figure 31: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
DS312 (v4.2) December 14, 2018
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Product Specification
37
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