Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 26
SLICEM
D
16x1
LUT
RAM
(Read/
Write)
SPO
A[3:0]
Optional
Register
WE
WCLK
DPO
16x1
LUT
RAM
(Read
Only)
DPRA[3:0]
Optional
Register
DS312-2_41_021305
Figure 26: RAM16X1D Dual-Port Usage
X-Ref Target - Figure 27
Table 19: Distributed RAM Signals
Signal Description
WCLK
RAM16X1D
WE
D
WCLK
SPO
DPO
The clock is used for synchronous writes. The
data and the address input pins have setup
times referenced to the WCLK pin. Active on
the positive edge by default with built-in
programmable polarity.
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3
WE
The enable pin affects the write functionality of
the port. An inactive Write Enable prevents
any writing to memory cells. An active Write
Enable causes the clock edge to write the data
input signal to the memory location pointed to
by the address inputs. Active High by default
with built-in programmable polarity.
DS312-2_42_021305
Figure 27: Dual-Port RAM Component
A0, A1, A2, A3 The address inputs select the memory cells for
Table 18: Dual-Port RAM Function
(A4, A5)
read or write. The width of the port determines
the required address inputs.
Inputs
Outputs
WE (mode)
0 (read)
1 (read)
1 (read)
1 (write)
1 (read)
WCLK
D
X
X
X
D
X
SPO
DPO
D
The data input provides the new data value to
be written into the RAM.
X
0
1
↑
↓
data_a
data_a
data_a
D
data_d
data_d
data_d
data_d
data_d
O, SPO, and
DPO
The data output O on single-port RAM or the
SPO and DPO outputs on dual-port RAM
reflects the contents of the memory cells
referenced by the address inputs. Following an
active write clock edge, the data out (O or
SPO) reflects the newly written data.
data_a
Notes:
The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
for RAM is all zeros. If the WE is held Low, the element can
be considered a ROM. The ROM function is possible even
in the SLICEL.
1. data_a = word addressed by bits A3-A0.
2. data_d = word addressed by bits DPRA3-DPRA0.
The global write enable signal, GWE, is asserted
automatically at the end of device configuration to enable all
writable elements. The GWE signal guarantees that the
DS312 (v4.2) December 14, 2018
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Product Specification
33
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