Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 24
Storage Elements
LUT
COUT
Am
Bn+1
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive transparent latch,
provides a means for synchronizing data to a clock signal,
among other uses. The storage elements in the top and
bottom portions of the slice are called FFY and FFX,
respectively. FFY has a fixed multiplexer on the D input
selecting either the combinatorial output Y or the bypass
signal BY. FFX selects between the combinatorial output X
or the bypass signal BX.
Am+1
Bn
Pm+1
MULT_AND
CIN
DS312-2_39_021305
Figure 24: Using the MULT_AND for Multiplication in
Carry Logic
The functionality of a slice storage element is identical to
that described earlier for the I/O storage elements. All
signals have programmable polarity; the default active-High
function is described.
The MULT_AND is useful for small multipliers. Larger
multipliers can be built using the dedicated 18x18 multiplier
blocks (see Dedicated Multipliers).
Table 15: Storage Element Signals
Signal
Description
D
Input. For a flip-flop data on the D input is loaded when R and S (or CLR and PRE) are Low and CE is High during the
Low-to-High clock transition. For a latch, Q reflects the D input while the gate (G) input and gate enable (GE) are High and R
and S (or CLR and PRE) are Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The
data on the Q output of the latch remains unchanged as long as G or GE remains Low.
Q
Output. Toggles after the Low-to-High clock transition for a flip-flop and immediately for a latch.
Clock for edge-triggered flip-flops.
C
G
Gate for level-sensitive latches.
CE
GE
S
Clock Enable for flip-flops.
Gate Enable for latches.
Synchronous Set (Q = High). When the S input is High and R is Low, the flip-flop is set, output High, during the Low-to-High
clock (C) transition. A latch output is immediately set, output High.
R
Synchronous Reset (Q = Low); has precedence over Set.
PRE
Asynchronous Preset (Q = High). When the PRE input is High and CLR is Low, the flip-flop is set, output High, during the
Low-to-High clock (C) transition. A latch output is immediately set, output High.
CLR
SR
Asynchronous Clear (Q = Low); has precedence over Preset to reset Q output Low
CLB input for R, S, CLR, or PRE
REV
CLB input for opposite of SR. Must be asynchronous or synchronous to match SR.
The control inputs R, S, CE, and C are all shared between
the two flip-flops in a slice.
Table 16: FD Flip-Flop Functionality with Synchronous
Reset, Set, and Clock Enable
X-Ref Target - Figure 25
Inputs
Outputs
S
R
1
0
0
0
0
S
X
1
0
0
0
CE
X
D
X
X
X
1
C
↑
↑
X
↑
↑
Q
FDRSE
0
D
CE
C
Q
X
1
0
No Change
R
1
1
0
DS312-2_40_021305
1
0
Figure 25: FD Flip-Flop Component with Synchronous
Reset, Set, and Clock Enable
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
