Spartan-3E FPGA Family: Functional Description
Table 22: Port Aspect Ratios
Total Data
Path Width
(w bits)
DI/DO Data
Bus Width
DIP/DOP
ADDR
No. of
Block RAM
Capacity
DI/DO
[w-p-1:0]
DIP/DOP
[p-1:0]
ADDR
[r-1:0]
Parity Bus
Bus Width
Addressable
(w-p bits)(1) Width (p bits)
(r bits)(2)
Locations (n)(3)
(w*n bits)(4)
1
2
1
2
0
0
0
1
2
4
14
13
12
11
10
9
[0:0]
[1:0]
-
[13:0]
[12:0]
[11:0]
[10:0]
[9:0]
16,384
8,192
4,096
2,048
1,024
512
16,384
16,384
16,384
18,432
18,432
18,432
-
4
4
[3:0]
-
9
8
[7:0]
[0:0]
[1:0]
[3:0]
18
36
16
32
[15:0]
[31:0]
[8:0]
Notes:
1. The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
2. The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log9(2)].
3. The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2 .
4. The product of w and n yields the total block RAM capacity.
r
If the data bus width of Port A differs from that of Port B, the
block RAM automatically performs a bus-matching function
as described in Figure 31. When data is written to a port
with a narrow bus and then read from a port with a wide bus,
the latter port effectively combines “narrow” words to form
“wide” words. Similarly, when data is written into a port with
a wide bus and then read from a port with a narrow bus, the
latter port divides “wide” words to form “narrow” words.
Parity bits are not available if the data port width is
configured as x4, x2, or x1. For example, if a x36 data word
(32 data, 4 parity) is addressed as two x18 halfwords (16
data, 2 parity), the parity bits associated with each data byte
are mapped within the block RAM to the appropriate parity
bits. The same effect happens when the x36 data word is
mapped as four x9 words.
DS312 (v4.2) December 14, 2018
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Product Specification
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